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data sheet preliminary 492 - channel source driver with power circuit for 16.7m colors asg tft-lcd panel oct. 26. 2004 ver. 0.1 prepared by checked by approved by seung-gun, lee veriwell@samsung.com byoung-ha, kim bhkim21@samsung.com yhong-deug, ma yd.ma@samsung.com system lsi division semiconductor business samsung electronics co., ltd. contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written p ermission of lcd driver ic team. S6F2002
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 2 S6F2002 specification revision history version content author date 0.0 new release k.m.kim s.h.kim b.h.han august 30, 2004 0.1 p.5 introduction comment revised. p.7 block diagram revised. b.h.han october 26, 2004
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 3 contents introduction ................................................................................................................... .....................................5 features....................................................................................................................... ..........................................6 block diagram .................................................................................................................. ............................ 7 pad configuration .............................................................................................................. ....................... 8 pad design information......................................................................................................... ................... 9 align key information.......................................................................................................... ................... 11 pad coordinates ................................................................................................................ ....................... 12 pin description................................................................................................................ ........................... 17 power supply configuration ..................................................................................................... ................22 case 1. dual power supply system 1............................................................................................. .... 22 case 2. dual power supply system 2............................................................................................. .... 23 case 3. single power supply system ............................................................................................. ... 24 functional description......................................................................................................... ........................25 system interface ............................................................................................................... ....................... 25 external interface (rgb-i/f) ................................................................................................... .............. 25 grayscale voltag e generator .................................................................................................... ...... 25 display timing control......................................................................................................... .................. 25 liquid crystal display driver circuit .......................................................................................... .... 25 power generation circuit ....................................................................................................... ............. 25 description of power generation circuit .................................................................................... 26 pattern diagram of th e voltage setting ...................................................................................... 27 instructions................................................................................................................... ....................................28 outline........................................................................................................................ ................................... 28 instruction table .............................................................................................................. ....................... 29 instruction descriptions ....................................................................................................... .............. 30 index (ir) ..................................................................................................................... ................................... 30 status r ead (sr)............................................................................................................... .......................... 30 id read (r00h) ................................................................................................................. .............................. 30 display interface control (r01h) ............................................................................................... ....... 31 display data control (r02h) .................................................................................................... ............. 33 entry mode (r03h).............................................................................................................. ........................ 34 gate control 1 (r04h) .......................................................................................................... .................... 36 gate control2 (r05h) ........................................................................................................... .................... 37 display control1 (r06h)........................................................................................................ .................. 39 display control2 (r07h)........................................................................................................ .................. 39 source output timing control (r08h) ............................................................................................ .. 40 power control 1 (r09h) ......................................................................................................... ................. 41 power control 2 (r0ah) ......................................................................................................... ................. 43 gamma control (r10h to r19h) ................................................................................................... .......... 45 reset function ................................................................................................................. .................................46 instruction set initialization ................................................................................................. ............. 46 output pin initialization...................................................................................................... ................... 46
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 4 interface specification........................................................................................................ .........................47 system interface : ser ial data transfer .......................................................................................4 7 procedure for transfer on clock syn chronized serial bus interface ........................48 24-bit interface ............................................................................................................... ...........................49 8-bit interface ................................................................................................................ ............................49 sync mode interface [24-bit] ................................................................................................... ..............50 sync mode interface [8-bit] .................................................................................................... ...............51 de mode interface [24-bit] ..................................................................................................... .................52 de mode interface [8-bit] ...................................................................................................... ..................53 display signal timing .......................................................................................................... ............................54 display timing in 1 frame ...................................................................................................... ..................54 display timing in 1 horizontal line............................................................................................ .........55 amorphous-silicon gate tft?lcd panel control ..............................................................................56 output signals ................................................................................................................. ..........................56 normal asg (nmd=0)............................................................................................................. ......................56 double asg (nmd=1) ............................................................................................................. ......................57 gamma adjustment function...................................................................................................... .................58 structure of grayscale amplifier............................................................................................... ...........59 gamma adjustment register ...................................................................................................... .................61 gradient adjusting resistor.................................................................................................... ...........61 reference adjusting resistor ................................................................................................... ........61 amplitude adjust ing resistor................................................................................................... ..........61 micro-adjusting resistor ....................................................................................................... ..............61 ladder resistor network / 8 to 1 selector ...................................................................................... ...63 variable r esist or .............................................................................................................. .......................63 the 8 to 1 selector............................................................................................................ .......................64 power supply setup flow ........................................................................................................ ....................70 instruction setup flow......................................................................................................... ........................71 display on / off sequence ...................................................................................................... ...............71 stand-by mode in / out sequence................................................................................................ ........72 n-raster-row reversed ac drive ................................................................................................. .............73 ac timing ...................................................................................................................... .........................................74 electrical specifications ...................................................................................................... ......................75 absolute maximum ratings....................................................................................................... .............75 dc characteristics ............................................................................................................. .....................76 ac characteristics ............................................................................................................. .....................78 amorphous-silicon gate level shifter........................................................................................... .81 data-shift direction settings.................................................................................................. ...................82 channel selection setting ...................................................................................................... .............82 master-slave configuration setting............................................................................................. ..83 ito / fpc application example .................................................................................................. ....................84 notice......................................................................................................................... ............................................86
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 5 introduction ? S6F2002 is a single or dual chip solution for amorphous-si-gate tft-lcd panel : source driver, gate-less level shifter and power circuits are integrated on one chip. S6F2002 can display up to 164-rgb x 240-dot graphics on 16.7m-color tft-lcd panel. specially, S6F2002 supports amorphous si tft-lcd panel. ? there are two kinds of interfaces in terms of data type. in case of display data, the S6F2002 offers a flexible 24-/8-bits high speed bus interface for transferring the 16.7m-color display data and supports a serial peripheral interface (spi) for transferring the control signals to set register value of driver ic. ? S6F2002 has various functions for reducing power consumption of lcd system. S6F2002 can be operated as low as 1.8v operating voltage. internal vcom signal generator which outputs tft-lcd counter-electrode driving signals, voltage follower circuits and accurate potentiometer for driving data lines of lcd panel are embedded. ? S6F2002 employs display-data digital-signal-processing unit to accomplish a tiny chip size. display data input via 24-/8-bits bus interface is compressed into 18-/6-bits data by real-time dsp algorithm. as a result, S6F2002 can receive 24-/8-bits display data transferred from mpu or ap and display 16.7m color images without losing color depth or original display information by unique digital-data processing. ? S6F2002 is suitable for any small or intermediate-sized mobile display solutions requiring long-term driving capability such as digital still cameras, digital cellular phones and personal multimedia player, etc.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 6 features ? 164-rgb x 240-dot amorphous si -gate tft-lcd driver ic for 16,777 ,216 colors (492ch-source driver). ? 24-/8- bits rgb interface and serial peripheral interface (spi) ? supporting sync mode / de mode data transfer system ? supporting delta / stripe pixel panel ? adjustable color-display control functions ? 16,777,216 colors can be displayed at the same time (gamma adjust included) ? supporting dual / single chip solution (master / slave operation is selectable in 2-driver system) ? supporting low-power operation : ? power-save functions such as standby mode, external vcom mode. ? voltage followers to decrease direct current flow in the lcd drive bleeder-resistors ? employing equalizing function for the charge-sharing between vcom circuits and source driver. ? frame/ 1- /2- raster row inversion driving ? structure for tft-display retention volume (cst structure) ? internal power supply circuit : ? internal vcl / vgoff generator for vcom blocks and gate level shifter circuits. ? internal power regulator is included for low-power consumption. ? adjustable vcomout amplitude: the amplitude of vcomout is determined by vcomh / vcoml voltages. vcomh / vcoml voltages are directly designated by vcm4-0 & vdv4-0 register value, respectively. 31-level precise digital potentiometers are also employed to set vcomh& vcoml. ? operating voltages : ? applying voltage ? vdd to vss = 1.8 to 2.5 v (non-regulating) : supply voltage range for logic circuit ? non-regulated a) vdd3 to vss = 2.5 to 3.3 v (regulating) : supply voltage range for logic circuit ? regulated b) vdd3 to vss = 1.8 to 3.3 v (logic interface) : supply voltage range for logic signal interface ? vci to vss = 2.5 to 3.3 v : supply voltage range for analog function block ? avdd to vss = 4.0 to 5.0 v : supply voltage range for liquid crystal driver circuits ? vgh to vss = ? vgl to vss = ? generated voltage ? for the analog block: |vcl| = 0.2x|vgl| : generated power for internal analog block. rvdd = 2.0 v fixed : generated power for internal logic block. ? for the gate driver: |vgoff| = 0.7x |vgl| : negative reference for asg level shifter block. |vgh-vgoff| (max) = 25.0 v ? for the tft-lcd counter electrode: vcomout amplitude (max) = 5.5 v vcomh to vss = 3.0 to 4.5 v vcoml to vss = -1.0 to 1.0 v ? released package type : cog only ? S6F2002 offers only a cog package type. film type package such as user-cof is not available.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 7 block diagram serial peripheral i/f asg-driving level shifter control register decoding level shifter control avdd vgs agnd avss vcomh vgh stv_r stv_l vcoml scl id sdi 492 channel source drivers m/ac circuit line latch circuit 24- / 8-bits rgb i/f shift registers pd<23:0> enable dotclk 64 lsenl lsenr grayscale voltage generator gamma adjustment circuit built-in power supply circuit display timing control vcl vdd3 vdd vsso csb vci rvdd rvdd generator ckvb_l resetb vss vcomout vgl vgoff ckv_r ckvb_r ckv_l 2952 2952 2952 24 .. .. .. .. s492 s491 s490 s3 s2 s1 .. .. .. .. ms dssel hsync vsync dsp unit 18 figure 1. block diagram
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 8 pad configuration figure 2. pad configuration
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 9 pad design information figure 3. bump information ? straight input pad figure 4. bump information ? staggered output pad
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 10 table 1. mechanical pad dimension size items pad name. x y unit chip size (with scribe lane : 100um) - 13,600 1,300 chip thickness - 450 +/-10 1 to 160 (input pad) 80 161 to 664 (output pad, even number) 52 pad pitch 161 to 664 (output pad, odd number) 52 input pad 54 +/-3 100 +/-3 bumped pad size (top) output pad 26 +/-3 85 +/-3 bumped pad height all pads 15(typ.) +/-3 um
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 11 align key information figure 5. cog align key layout figure 6. cog align key information
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 12 pad coordinates table 2. pad coordinates no name x y no name x y no name x y 1 dummy<1> -6360 -531 51 vgs -2360 -531 101 vss 1640 -531 2 dummy<2> -6280 -531 52 vgs -2280 -531 102 lsenl 1720 -531 3 stv_l -6200 -531 53 vss -2200 -531 103 vdd3 1800 -531 4 stv_l -6120 -531 54 id -2120 -531 104 lsenr 1880 -531 5 vgh -6040 -531 55 vdd3 -2040 -531 105 vss 1960 -531 6 vgh -5960 -531 56 ms -1960 -531 106 avdd 2040 -531 7 vgh -5880 -531 57 vss -1880 -531 107 avdd 2120 -531 8 vgh -5800 -531 58 dssel -1800 -531 108 avdd 2200 -531 9 vgl -5720 -531 59 vdd3 -1720 -531 109 avdd 2280 -531 10 vgl -5640 -531 60 m -1640 -531 110 avdd 2360 -531 11 vgl -5560 -531 61 vss -1560 -531 111 gvdd 2440 -531 12 vgl -5480 -531 62 test -1480 -531 112 gvdd 2520 -531 13 ckv_l -5400 -531 63 tsi<2> -1400 -531 113 vdd3 2600 -531 14 ckv_l -5320 -531 64 tsi<1> -1320 -531 114 vdd3 2680 -531 15 ckv_l -5240 -531 65 tsi<0> -1240 -531 115 vdd3 2760 -531 16 ckvb_l -5160 -531 66 tso<1> -1160 -531 116 vdd 2840 -531 17 ckvb_l -5080 -531 67 tso<0> -1080 -531 117 vdd 2920 -531 18 ckvb_l -5000 -531 68 resetb -1000 -531 118 vdd 3000 -531 19 vcomout -4920 -531 69 csb -920 -531 119 vdd 3080 -531 20 vcomout -4840 -531 70 scl -840 -531 120 rvdd 3160 -531 21 vcomout -4760 -531 71 sdi -760 -531 121 rvdd 3240 -531 22 vcomout -4680 -531 72 pd<0> -680 -531 122 rvdd 3320 -531 23 vcl -4600 -531 73 pd<1> -600 -531 123 rvdd 3400 -531 24 vcl -4520 -531 74 pd<2> -520 -531 124 rvdd_ref 3480 -531 25 vcl -4440 -531 75 pd<3> -440 -531 125 vci 3560 -531 26 vcl -4360 -531 76 pd<4> -360 -531 126 vci 3640 -531 27 vgoff -4280 -531 77 pd<5> -280 -531 127 vci 3720 -531 28 vgoff -4200 -531 78 pd<6> -200 -531 128 vci 3800 -531 29 vgoff -4120 -531 79 pd<7> -120 -531 129 vcoml 3880 -531 30 vgoff -4040 -531 80 pd<8> -40 -531 130 vcoml 3960 -531 31 agnd -3960 -531 81 pd<9> 40 -531 131 vcoml 4040 -531 32 agnd -3880 -531 82 pd<10> 120 -531 132 vcoml 4120 -531 33 agnd -3800 -531 83 pd<11> 200 -531 133 vcomh 4200 -531 34 agnd -3720 -531 84 pd<12> 280 -531 134 vcomh 4280 -531 35 agnd -3640 -531 85 pd<13> 360 -531 135 vcomh 4360 -531 36 vss -3560 -531 86 pd<14> 440 -531 136 vcomh 4440 -531 37 vss -3480 -531 87 pd<15> 520 -531 137 contact1 4520 -531 38 vss -3400 -531 88 vss 600 -531 138 contact2 4600 -531 39 vss -3320 -531 89 pd<16> 680 -531 139 vcomout 4680 -531 40 vss -3240 -531 90 pd<17> 760 -531 140 vcomout 4760 -531 41 vss -3160 -531 91 pd<18> 840 -531 141 vcomout 4840 -531 42 vss -3080 -531 92 pd<19> 920 -531 142 vcomout 4920 -531 43 vss -3000 -531 93 pd<20> 1000 -531 143 ckvb_r 5000 -531 44 vss -2920 -531 94 pd<21> 1080 -531 144 ckvb_r 5080 -531 45 vss -2840 -531 95 pd<22> 1160 -531 145 ckvb_r 5160 -531 46 avss -2760 -531 96 pd<23> 1240 -531 146 ckv_r 5240 -531 47 avss -2680 -531 97 enable 1320 -531 147 ckv_r 5320 -531 48 avss -2600 -531 98 hsync 1400 -531 148 ckv_r 5400 -531 49 avss -2520 -531 99 vsync 1480 -531 149 vgl 5480 -531 50 avss -2440 -531 100 dotclk 1560 -531 150 vgl 5560 -531
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 13 table 3. pad coordinates (continued) no name x y no name x y no name x y 151 vgl 5640 -531 201 s<458> 5499 538 251 s<408> 4199 538 152 vgl 5720 -531 202 s<457> 5473 413 252 s<407> 4173 413 153 vgh 5800 -531 203 s<456> 5447 538 253 s<406> 4147 538 154 vgh 5880 -531 204 s<455> 5421 413 254 s<405> 4121 413 155 vgh 5960 -531 205 s<454> 5395 538 255 s<404> 4095 538 156 vgh 6040 -531 206 s<453> 5369 413 256 s<403> 4069 413 157 stv_r 6120 -531 207 s<452> 5343 538 257 s<402> 4043 538 158 stv_r 6200 -531 208 s<451> 5317 413 258 s<401> 4017 413 159 dummy<3> 6280 -531 209 s<450> 5291 538 259 s<400> 3991 538 160 dummy<4> 6360 -531 210 s<449> 5265 413 260 s<399> 3965 413 161 dummy<5> 6591 538 211 s<448> 5239 538 261 s<398> 3939 538 162 dummy<6> 6565 413 212 s<447> 5213 413 262 s<397> 3913 413 163 dummy<7> 6513 538 213 s<446> 5187 538 263 s<396> 3887 538 164 dummy<8> 6487 413 214 s<445> 5161 413 264 s<395> 3861 413 165 dummy<9> 6435 538 215 s<444> 5135 538 265 s<394> 3835 538 166 dummy<10> 6409 413 216 s<443> 5109 413 266 s<393> 3809 413 167 s<492> 6383 538 217 s<442> 5083 538 267 s<392> 3783 538 168 s<491> 6357 413 218 s<441> 5057 413 268 s<391> 3757 413 169 s<490> 6331 538 219 s<440> 5031 538 269 s<390> 3731 538 170 s<489> 6305 413 220 s<439> 5005 413 270 s<389> 3705 413 171 s<488> 6279 538 221 s<438> 4979 538 271 s<388> 3679 538 172 s<487> 6253 413 222 s<437> 4953 413 272 s<387> 3653 413 173 s<486> 6227 538 223 s<436> 4927 538 273 s<386> 3627 538 174 s<485> 6201 413 224 s<435> 4901 413 274 s<385> 3601 413 175 s<484> 6175 538 225 s<434> 4875 538 275 s<384> 3575 538 176 s<483> 6149 413 226 s<433> 4849 413 276 s<383> 3549 413 177 s<482> 6123 538 227 s<432> 4823 538 277 s<382> 3523 538 178 s<481> 6097 413 228 s<431> 4797 413 278 s<381> 3497 413 179 s<480> 6071 538 229 s<430> 4771 538 279 s<380> 3471 538 180 s<479> 6045 413 230 s<429> 4745 413 280 s<379> 3445 413 181 s<478> 6019 538 231 s<428> 4719 538 281 s<378> 3419 538 182 s<477> 5993 413 232 s<427> 4693 413 282 s<377> 3393 413 183 s<476> 5967 538 233 s<426> 4667 538 283 s<376> 3367 538 184 s<475> 5941 413 234 s<425> 4641 413 284 s<375> 3341 413 185 s<474> 5915 538 235 s<424> 4615 538 285 s<374> 3315 538 186 s<473> 5889 413 236 s<423> 4589 413 286 s<373> 3289 413 187 s<472> 5863 538 237 s<422> 4563 538 287 s<372> 3263 538 188 s<471> 5837 413 238 s<421> 4537 413 288 s<371> 3237 413 189 s<470> 5811 538 239 s<420> 4511 538 289 s<370> 3211 538 190 s<469> 5785 413 240 s<419> 4485 413 290 s<369> 3185 413 191 s<468> 5759 538 241 s<418> 4459 538 291 s<368> 3159 538 192 s<467> 5733 413 242 s<417> 4433 413 292 s<367> 3133 413 193 s<466> 5707 538 243 s<416> 4407 538 293 s<366> 3107 538 194 s<465> 5681 413 244 s<415> 4381 413 294 s<365> 3081 413 195 s<464> 5655 538 245 s<414> 4355 538 295 s<364> 3055 538 196 s<463> 5629 413 246 s<413> 4329 413 296 s<363> 3029 413 197 s<462> 5603 538 247 s<412> 4303 538 297 s<362> 3003 538 198 s<461> 5577 413 248 s<411> 4277 413 298 s<361> 2977 413 199 s<460> 5551 538 249 s<410> 4251 538 299 s<360> 2951 538 200 s<459> 5525 413 250 s<409> 4225 413 300 s<359> 2925 413
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 14 table 4. pad coordinates (continued) no name x y no name x y no name x y 301 s<358> 2899 538 351 s<308> 1599 538 401 s<258> 299 538 302 s<357> 2873 413 352 s<307> 1573 413 402 s<257> 273 413 303 s<356> 2847 538 353 s<306> 1547 538 403 s<256> 247 538 304 s<355> 2821 413 354 s<305> 1521 413 404 s<255> 221 413 305 s<354> 2795 538 355 s<304> 1495 538 405 s<254> 195 538 306 s<353> 2769 413 356 s<303> 1469 413 406 s<253> 169 413 307 s<352> 2743 538 357 s<302> 1443 538 407 s<252> 143 538 308 s<351> 2717 413 358 s<301> 1417 413 408 s<251> 117 413 309 s<350> 2691 538 359 s<300> 1391 538 409 s<250> 91 538 310 s<349> 2665 413 360 s<299> 1365 413 410 s<249> 65 413 311 s<348> 2639 538 361 s<298> 1339 538 411 s<248> 39 538 312 s<347> 2613 413 362 s<297> 1313 413 412 s<247> 13 413 313 s<346> 2587 538 363 s<296> 1287 538 413 s<246> -13 538 314 s<345> 2561 413 364 s<295> 1261 413 414 s<245> -39 413 315 s<344> 2535 538 365 s<294> 1235 538 415 s<244> -65 538 316 s<343> 2509 413 366 s<293> 1209 413 416 s<243> -91 413 317 s<342> 2483 538 367 s<292> 1183 538 417 s<242> -117 538 318 s<341> 2457 413 368 s<291> 1157 413 418 s<241> -143 413 319 s<340> 2431 538 369 s<290> 1131 538 419 s<240> -169 538 320 s<339> 2405 413 370 s<289> 1105 413 420 s<239> -195 413 321 s<338> 2379 538 371 s<288> 1079 538 421 s<238> -221 538 322 s<337> 2353 413 372 s<287> 1053 413 422 s<237> -247 413 323 s<336> 2327 538 373 s<286> 1027 538 423 s<236> -273 538 324 s<335> 2301 413 374 s<285> 1001 413 424 s<235> -299 413 325 s<334> 2275 538 375 s<284> 975 538 425 s<234> -325 538 326 s<333> 2249 413 376 s<283> 949 413 426 s<233> -351 413 327 s<332> 2223 538 377 s<282> 923 538 427 s<232> -377 538 328 s<331> 2197 413 378 s<281> 897 413 428 s<231> -403 413 329 s<330> 2171 538 379 s<280> 871 538 429 s<230> -429 538 330 s<329> 2145 413 380 s<279> 845 413 430 s<229> -455 413 331 s<328> 2119 538 381 s<278> 819 538 431 s<228> -481 538 332 s<327> 2093 413 382 s<277> 793 413 432 s<227> -507 413 333 s<326> 2067 538 383 s<276> 767 538 433 s<226> -533 538 334 s<325> 2041 413 384 s<275> 741 413 434 s<225> -559 413 335 s<324> 2015 538 385 s<274> 715 538 435 s<224> -585 538 336 s<323> 1989 413 386 s<273> 689 413 436 s<223> -611 413 337 s<322> 1963 538 387 s<272> 663 538 437 s<222> -637 538 338 s<321> 1937 413 388 s<271> 637 413 438 s<221> -663 413 339 s<320> 1911 538 389 s<270> 611 538 439 s<220> -689 538 340 s<319> 1885 413 390 s<269> 585 413 440 s<219> -715 413 341 s<318> 1859 538 391 s<268> 559 538 441 s<218> -741 538 342 s<317> 1833 413 392 s<267> 533 413 442 s<217> -767 413 343 s<316> 1807 538 393 s<266> 507 538 443 s<216> -793 538 344 s<315> 1781 413 394 s<265> 481 413 444 s<215> -819 413 345 s<314> 1755 538 395 s<264> 455 538 445 s<214> -845 538 346 s<313> 1729 413 396 s<263> 429 413 446 s<213> -871 413 347 s<312> 1703 538 397 s<262> 403 538 447 s<212> -897 538 348 s<311> 1677 413 398 s<261> 377 413 448 s<211> -923 413 349 s<310> 1651 538 399 s<260> 351 538 449 s<210> -949 538 350 s<309> 1625 413 400 s<259> 325 413 450 s<209> -975 413
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 15 table 5. pad coordinates (continued) no name x y no name x y no name x y 451 s<208> -1001 538 501 s<158> -2301 538 551 s<108> -3601 538 452 s<207> -1027 413 502 s<157> -2327 413 552 s<107> -3627 413 453 s<206> -1053 538 503 s<156> -2353 538 553 s<106> -3653 538 454 s<205> -1079 413 504 s<155> -2379 413 554 s<105> -3679 413 455 s<204> -1105 538 505 s<154> -2405 538 555 s<104> -3705 538 456 s<203> -1131 413 506 s<153> -2431 413 556 s<103> -3731 413 457 s<202> -1157 538 507 s<152> -2457 538 557 s<102> -3757 538 458 s<201> -1183 413 508 s<151> -2483 413 558 s<101> -3783 413 459 s<200> -1209 538 509 s<150> -2509 538 559 s<100> -3809 538 460 s<199> -1235 413 510 s<149> -2535 413 560 s<99> -3835 413 461 s<198> -1261 538 511 s<148> -2561 538 561 s<98> -3861 538 462 s<197> -1287 413 512 s<147> -2587 413 562 s<97> -3887 413 463 s<196> -1313 538 513 s<146> -2613 538 563 s<96> -3913 538 464 s<195> -1339 413 514 s<145> -2639 413 564 s<95> -3939 413 465 s<194> -1365 538 515 s<144> -2665 538 565 s<94> -3965 538 466 s<193> -1391 413 516 s<143> -2691 413 566 s<93> -3991 413 467 s<192> -1417 538 517 s<142> -2717 538 567 s<92> -4017 538 468 s<191> -1443 413 518 s<141> -2743 413 568 s<91> -4043 413 469 s<190> -1469 538 519 s<140> -2769 538 569 s<90> -4069 538 470 s<189> -1495 413 520 s<139> -2795 413 570 s<89> -4095 413 471 s<188> -1521 538 521 s<138> -2821 538 571 s<88> -4121 538 472 s<187> -1547 413 522 s<137> -2847 413 572 s<87> -4147 413 473 s<186> -1573 538 523 s<136> -2873 538 573 s<86> -4173 538 474 s<185> -1599 413 524 s<135> -2899 413 574 s<85> -4199 413 475 s<184> -1625 538 525 s<134> -2925 538 575 s<84> -4225 538 476 s<183> -1651 413 526 s<133> -2951 413 576 s<83> -4251 413 477 s<182> -1677 538 527 s<132> -2977 538 577 s<82> -4277 538 478 s<181> -1703 413 528 s<131> -3003 413 578 s<81> -4303 413 479 s<180> -1729 538 529 s<130> -3029 538 579 s<80> -4329 538 480 s<179> -1755 413 530 s<129> -3055 413 580 s<79> -4355 413 481 s<178> -1781 538 531 s<128> -3081 538 581 s<78> -4381 538 482 s<177> -1807 413 532 s<127> -3107 413 582 s<77> -4407 413 483 s<176> -1833 538 533 s<126> -3133 538 583 s<76> -4433 538 484 s<175> -1859 413 534 s<125> -3159 413 584 s<75> -4459 413 485 s<174> -1885 538 535 s<124> -3185 538 585 s<74> -4485 538 486 s<173> -1911 413 536 s<123> -3211 413 586 s<73> -4511 413 487 s<172> -1937 538 537 s<122> -3237 538 587 s<72> -4537 538 488 s<171> -1963 413 538 s<121> -3263 413 588 s<71> -4563 413 489 s<170> -1989 538 539 s<120> -3289 538 589 s<70> -4589 538 490 s<169> -2015 413 540 s<119> -3315 413 590 s<69> -4615 413 491 s<168> -2041 538 541 s<118> -3341 538 591 s<68> -4641 538 492 s<167> -2067 413 542 s<117> -3367 413 592 s<67> -4667 413 493 s<166> -2093 538 543 s<116> -3393 538 593 s<66> -4693 538 494 s<165> -2119 413 544 s<115> -3419 413 594 s<65> -4719 413 495 s<164> -2145 538 545 s<114> -3445 538 595 s<64> -4745 538 496 s<163> -2171 413 546 s<113> -3471 413 596 s<63> -4771 413 497 s<162> -2197 538 547 s<112> -3497 538 597 s<62> -4797 538 498 s<161> -2223 413 548 s<111> -3523 413 598 s<61> -4823 413 499 s<160> -2249 538 549 s<110> -3549 538 599 s<60> -4849 538 500 s<159> -2275 413 550 s<109> -3575 413 600 s<59> -4875 413
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 16 table 6. pad coordinates (continued) no name x y no name x y 601 s<58> -4901 538 651 s<8> -6201 538 602 s<57> -4927 413 652 s<7> -6227 413 603 s<56> -4953 538 653 s<6> -6253 538 604 s<55> -4979 413 654 s<5> -6279 413 605 s<54> -5005 538 655 s<4> -6305 538 606 s<53> -5031 413 656 s<3> -6331 413 607 s<52> -5057 538 657 s<2> -6357 538 608 s<51> -5083 413 658 s<1> -6383 413 609 s<50> -5109 538 659 dummy<11> -6409 538 610 s<49> -5135 413 660 dummy<12> -6435 413 611 s<48> -5161 538 661 dummy<13> -6487 538 612 s<47> -5187 413 662 dummy<14> -6513 413 613 s<46> -5213 538 663 dummy<15> -6565 538 614 s<45> -5239 413 664 dummy<16> -6591 413 615 s<44> -5265 538 616 s<43> -5291 413 617 s<42> -5317 538 618 s<41> -5343 413 619 s<40> -5369 538 620 s<39> -5395 413 621 s<38> -5421 538 622 s<37> -5447 413 623 s<36> -5473 538 624 s<35> -5499 413 625 s<34> -5525 538 626 s<33> -5551 413 627 s<32> -5577 538 628 s<31> -5603 413 629 s<30> -5629 538 630 s<29> -5655 413 631 s<28> -5681 538 632 s<27> -5707 413 633 s<26> -5733 538 634 s<25> -5759 413 635 s<24> -5785 538 636 s<23> -5811 413 637 s<22> -5837 538 638 s<21> -5863 413 639 s<20> -5889 538 640 s<19> -5915 413 641 s<18> -5941 538 642 s<17> -5967 413 643 s<16> -5993 538 644 s<15> -6019 413 645 s<14> -6045 538 646 s<13> -6071 413 647 s<12> -6097 538 648 s<11> -6123 413 649 s<10> -6149 538 650 s<9> -6175 413
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 17 pin description table 7. power supply pin description symbol i/o description vdd power system power supply for logic circuit block. as S6F2002 has internal power regulator, vdd range varies with each mode. non-regulated : +1.8 ~ +2.5 v regulated : +2.0 v fixed. (connecting rvdd) vdd3 power system power supply for logic interface signal. (vdd3: +1.8v~3.3v) vss power system ground level. (0v) agnd power system ground level for power circuit block. (0v) avss power system ground level for source driver circuit block. (0v) vci power system power supply for internal power generation circuit block. avdd power system power supply for source driver circuit block. gvdd i reference voltage for grayscale voltage generator, high level. connect this pin at avdd when in usual case. vgs i reference voltage for grayscale voltage generator, low level. connect this pin at avss when in usual case.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 18 table 8. power supply pin description (continued) symbol i/o description vcomout o a power supply for the tft- lcd panel counter electrode. connect this pin to the tft-lcd panel counter electrode. this output also contributes for equalizing function: when eq = ?high? period, all outputs of source driver (s1 to s492) are shorted to vcomout level (hi-z). vcomh o high level output voltage of vcomout signal. output voltage level can be established directly by vcm4-0 register setting. attach a capacitor to this pin for stabilization. vcoml o low level output voltage of vcomout signal. output voltage level can be established directly by vdv4-0 register setting. attach a capacitor to this pin for stabilization. vgh power a positive power supply for level shifter circuit blocks which output amorphous-silicon gate driving signals such as ckv_l/r, ckvb_l/r, stv_l/r. vgl power a negative power supply for level shifter circuit blocks which output amorphous-silicon gate driving signals such as ckv_l/r, ckvb_l/r, stv_l/r. it is also used as a power supply for vcl & vgoff generation circuit block. vgoff o a voltage output pin for amorphous-silicon gate driver signals which comes from integrated gate level shifter circuits. vgoff indicates a negative voltage level for the gate-off signal. connect a capacitor for stabilization. vcl o a voltage output pin for vcoml generation circuit block. vcl is used as a negative power supply pin for vcoml generator. connect a capacitor for stabilization.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 19 table 9. interface pin description symbol i/o description id i id setting pin for a device code. csb i selects the S6F2002: low: S6F2002 is selected and can be accessed high: S6F2002 is not selected and cannot be accessed must be tied to vss level when not in use. scl i serial clock input pin for a clock-synchronous serial interface. sdi i serial data input pin for a clock-synchronous serial interface. dssel i select dual- / single- chip operation mode. low: operates in the single-chip configuration. high: operates in the dual-chip configuration. ms i select master / slave operation mode in dual-chip configuration. low: operates as a master driver high: operates as a slave driver note . in the single-chip configuration, ms should be fixed at ?l?, selected as a master driver. lsenl i output enable signal of asg level shifters on the left side. low: ckv_l / ckvb_l / stv_l outputs gate-off (vgoff) level. high: ckv_l / ckvb_l / stv_l outputs gate control signal traveling from vgh to vgoff. lsenr i output enable signal of asg level shifters on the right side. low: ckv_r / ckvb_r / stv_r outputs gate-off (vgoff) level. high: ckv_r / ckvb_r / stv_r outputs gate control signal traveling from vgh to vgoff. enable i data enabling signal for using de mode. vsync i synchronous signal of frame for using sync mode. hsync i synchronous signal of line for using sync mode. dotclk i dot clock signal. pd [23:0] i serves as a 24-bit data bus. 8-bit interface: pd [23:16] 24-bit interface: pd [23:0] unused pins must be connected to vdd3 or vss level.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 20 table 10. interface pin description (continued) symbol i/o description test i test mode entry pin. this pin is used only for test purpose at vendor-side. fixed at gnd level in user-configuration. tsi [2:0] i test mode selection pins. these pins are used only for test purpose at vendor-side. fixed at gnd level in user-configuration. tso [1:0] o test signal output pins. leave floating in user-configuration. vdd3o power vdd3 level used only for i/o pads: should be connected to vdd3. vsso power vss level used only for i/o pads: should be connected to vss. resetb i reset pins. initializes the lsi when low. must be reset after power-on. contact1 contact2 - pass-through pins. identical pins at input and output part that is connected without any internal circuitry.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 21 table 11. display pin description symbol i/o description s1 ? s492 o source driver output pins. s1, s4, s7, ... s(3n-2) : display red (r) (ss = 0) s2, s5, s8, ... s(3n-1) : display green (g) (ss = 0) s3, s6, s9, ... s(3n) : display blue (b) (ss = 0) stv_l stv_r o tft-lcd gate shift start pulse for amorphous-silicon gate panel. ckv_l ckv_r o tft-lcd gate shift clock for amorphous-silicon gate panel. ckvb_l ckvb_r o tft-lcd gate shift clock for amorphous-silicon gate panel. m o output pin for ac-cycle signal table 12. internal power regulator pin description symbol i/o description rvdd o internal generated power supply output so called regulated-vdd. when vdd3 exceeds 2.5v, vdd should be connected to rvdd instead of external vdd3 to protect internal logic circuit and to obtain low-power condition. attach a capacitor to this pin for stabilization. rvdd_ref i reference voltage input pin for generating vcomh / vcoml level. this pin should be connected to rvdd outputs.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 22 power supply configuration S6F2002 has internal power regulator named rvdd circuit. regulated voltage output is 2.0v. by use of this circuit block, damage on internal logic circuit by excessive power supply can be prohibited. furthermore, lower power consumption can be obtained either. detailed power connection example and application setup are depicted from figure.7 to figure.9 with various power levels which are applied. case 1. dual power supply system 1 rvdd regulator analog power 2.5v ~ 3.3v rvdd 2.0v vdd vci logic l / s gnd vcomh vcoml block rvdd_ref vdd3 internal logic logic i/o logic power 1.8v ~ 2.5v logic swing 1.8v ~ 2.5v figure 7. dual power supply system : vdd < 2.5v
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 23 case 2. dual power supply system 2 rvdd regulator analog power 2.5v ~ 3.3v 2.0v logic l / s gnd vcomh vcoml block internal logic logic power 2.5v ~ 3.3v logic swing 2.5v ~ 3.3v rvdd vdd vci rvdd_ref vdd3 logic i/o figure 8. dual power supply system : vdd > 2.5v
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 24 case 3. single power supply system rvdd regulator single power 2.5v ~ 3.3v 2.0v logic l / s gnd vcomh vcoml block internal logic logic swing 2.5v ~ 3.3v rvdd vdd vci rvdd_ref vdd3 logic i/o figure 9. single power supply system
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 25 functional description system interface the S6F2002 has a serial peripheral interface port (spi). this block receives instructions and transfers the data to the internal control register for power control, display control, gamma adjustment. (to control the power circuit, display circuit and gamma adjustment circuit.). table 13. register selection (serial peripheral interface) r/w bit rs bit operations 0 0 writes indexes into ir 1 0 reads internal status 0 1 writes into control registers 1 1 reads instructions external interface (rgb-i/f) the S6F2002 supports rgb interface as an external interface for motion picture display. rgb display data of one line(from s1 to s492) are latched to the data latch register through parallel data bus pd in orderly. if one line data is latched, data is transferred to the source driver amp and then the data of data latch register is displayed. grayscale voltage generator the grayscale voltage circuit generates lcd driver voltages which correspond to the grayscale levels as specified in the grayscale ? -adjusting resistor. 262,144 possible colors can be displayed at the same time. for details, see the ? -adjusting resistor. display timing control the timing generator generates the interface signals such as stv, ckv, ckvb through the embedded level shifter for amorphous-silicon gate driver. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 492 source drivers (s1 to s492). display pattern data are latched when 492-bit data have arrived. the latched data then enable the source drivers to generate drive waveform outputs. the ss bit can change the shift direction of 492-bit data by selecting an appropriate direction for the device-mounted configuration. power generation circuit power generation circuit generates vcl, vgoff, vcomh, vcoml and vcomout voltages which are related to display the tft-lcd panel.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 26 description of power generation circuit figure.10 shows a block diagram of reference power generating circuit of S6F2002. the vcom generation circuit consists of vcomh generation circuit, vcoml generation circuit and vcomout switching stage which drives counter-electrode of tft-lcd panel directly. vcomh generation circuit produces high level of vcom output by embedded voltage-adjustment circuit & voltage follower as an output stage. voltage level of vcomh is set by vcm4-0 register and is ranging from 3.0v to 4.5v. vcoml generation circuit produces low level of vcom output by embedded voltage-adjustment circuit & voltage follower as an output stage. voltage level of vcoml is set by vdv4-0 register and is ranging from -1.0v to 1.0v. there?s no relationship beween set values of vcomh & vcoml because they?re set by independent analog circuits. vcl & vgoff are generated from vgl voltage with some equations as follows: |vgoff| = 0.7x|vgl|, |vcl| = 0.2x|vgl|. vcl provides negative power supply for vcoml circuit. vgoff serves as a negative voltage reference for asg level shifter. rvdd vcomh vcomout vcoml vgoff rvdd_ref vcomh adjustment circuit vcomh output amplifier vcoml output amplifier vcoml adjustment circuit rvdd generation block (vref + buffer) vgoff generation block (divider + output amplifier) vcl vcl generation block (divider + output amplifier) vss vss vdd vci vss avdd vgl vss vss vgh gamma adjustment circuit grayscale generation circuit s1 - s492 ckv_l/r 492-channel source driver gate level shifter for asg panel ckvb_l/r stv_l/r figure 10. reference power generation block diagram notes: use the 1uf capacitor .
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 27 pattern diagram of the voltage setting the following figure shows a pattern diagram of the voltage settings. vgh ( typ. +18.0v ) avdd (4.0 - 5.0v) vcomh ( 3.0 ~ 4.5v) vcm [4:0] vcl vcoml ( -1.0 ~ 1.0v) vgoff vgl ( typ. -10.0v ) vgoff generation circuit ( 0.7*|vgl| ) vci (2.5v - 3.3v) vdd (1.8v ~ 2.5v) agnd / gnd (0v) note: 1. | vgoff - vgl | >= 3.0v when | vgh - vgoff | = 25.0v vcl generation circuit ( 0.2*|vgl| ) vdv [4:0] vcomout amplitude ( max. 5.5v ) vcomg vdd3 (1.8v ~ 3.3v) figure 11. pattern diagram of internal voltage setting
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 28 instructions outline the operation of the S6F2002 is determined by signals sent through serial peripheral interface. these signals include the register selection signal (rs), the read/write signal (r/w), and the internal 16-bit data bus signals (ib15 to ib0), make up the S6F2002 instructions. there are five categories of instructions that: - specify the index - read the status - control the display - control power management - set grayscale level for the internal grayscale palette table
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 29 instruction table reg no. ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 - id6 id5 id4 id3 id2 id1 id0 00h 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 01h im nmd ssmd 0 0 0 0 0 rev 0 0 nl4 nl3 nl2 nl1 nl0 02h 0 0 ds1 ds0 0 chs1 chs0 0 df1 df0 0 0 rgb1 rgb0 0 0 03h vpl hpl dpl epl 0 0 0 ss 0 0 0 0 0 0 stb 0 04h 0 clw2 clw1 clw0 0 0 0 0 0 0 gaon 0 sdr 0 0 0 05h nw1 nw0 0 dsc 0 0 0 gif fhn 0 ftn1 ftn0 0 0 fwi1 fwi0 06h 0 0 0 0 0 0 0 vbp8 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 07h 0 0 0 0 0 0 hbp9 hbp8 hbp7 hbp6 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 08h 0 0 0 sdt2 sdt1 sdt0 0 0 0 0 0 eq2 eq1 eq0 0 0 09h 0 exm 0 0 gon 0 poc 0 0 sap2 sap1 sap0 0 ap2 ap1 ap0 0ah 0 0 vcomg vdv4 vdv3 vdv2 vdv1 vdv0 0 0 0 vcm4 vcm3 vcm2 vcm1 vcm0 10h 0 0 0 0 0 prp12 prp11 prp10 0 0 0 0 0 prp02 prp01 prp00 11h 0 0 0 0 0 prn12 prn11 prn10 0 0 0 0 0 prn02 prn01 prn00 12h 0 0 0 vrp14 vrp13 vrp12 vrp11 vrp10 0 0 0 0 vrp03 vrp02 vrp01 vrp00 13h 0 0 0 vrn14 vrn13 vrn12 vrn11 vrn10 0 0 0 0 vrn03 vrn02 vrn01 vrn00 14h 0 0 0 0 0 pkp12 pkp11 pkp10 0 0 0 0 0 pkp02 pkp01 pkp00 15h 0 0 0 0 0 pkp32 pkp31 pkp30 0 0 0 0 0 pkp22 pkp21 pkp20 16h 0 0 0 0 0 pkp52 pkp51 pkp50 0 0 0 0 0 pkp42 pkp41 pkp40 17h 0 0 0 0 0 pkn12 pkn11 pkn10 0 0 0 0 0 pkn02 pkn01 pkn00 18h 0 0 0 0 0 pkn32 pkn31 pkn30 0 0 0 0 0 pkn22 pkn21 pkn20 19h 0 0 0 0 0 pkn52 pkn51 pkn50 0 0 0 0 0 pkn42 pkn41 pkn40
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 30 instruction descriptions ensure that you are aware of the assignments of instruction bits (ib15-0) for each interface that are illustrated below. index (ir) the index instruction specifies the control register indexes (r00h to r4fh). it sets the register number in the range of 0000000 to 1111111 in binary form. however, do not access to index register and instruction bit that is not allocated in index register. w0 *********id6id5id4id3id2id1id0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 w0 *********id6id5id4id3id2id1id0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 figure 12. index instruction status read (sr) the status read instruction reads the internal status of the S6F2002. l7?0: indicate the driving raster-row position where the liquid crystal display is being driven. r0 l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 r0 l7 l6 l5 l4 l3 l2 l1 l0 0 0 0 0 0 0 0 0 r/w rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 figure 13. status read instruction id read (r00h) the id read instruction reads the device index of S6F2002 : when perform this instruction, 2002h is read. 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 figure 14. id read instruction
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 31 display interface control (r01h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 im nmd ssmd 0 0 0 0 rev 0 0 nl4 nl3 nl2 nl1 nl1 figure 15. display interface control instruction im : specify the pd data weight. im = ?0? : 24bits interface im = ?1? : 8bits interface nmd : specify the asg format. nmd = ?0? : normal asg nmd = ?1? : double asg ssmd : specify the interface mode. ssmd = ?0? : sync mode ssmd = ?1? : de mode rev : reverses all character and graphics display sections . rev = ?0? : normally white panel rev = ?1? : normally black panel table 14. rev bit and source output level of displayed area source output level of displayed area rev data positive polarity negative polarity 0 6?b000000 m 6?b111111 v0 m v63 v63 m v0 1 6?b000000 m 6?b111111 v63 m v0 v0 m v63
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 32 nl4?0 : specify number of lines for the lcd drive. number of lines for the lcd drive can be adjusted for every eight raster-rows. the selected size should be larger than or equal to the panel size to be driven. table 15. nl bits and drive duty nl4 nl3 nl2 nl1 nl0 display size lcd raster rows gate- lines used 0 0 0 0 0 setting disabled setting disabled setting disabled 0 0 0 0 1 176rgb x 16 16 g1 to g16 0 0 0 1 0 176rgb x 24 24 g1 to g24 0 0 0 1 1 176rgb x 32 32 g1 to g32 0 0 1 0 0 176rgb x 40 40 g1 to g40 0 0 1 0 1 176rgb x 48 48 g1 to g48 0 0 1 1 0 176rgb x 56 56 g1 to g56 0 0 1 1 1 176rgb x 64 64 g1 to g64 0 1 0 0 0 176rgb x 72 72 g1 to g72 0 1 0 0 1 176rgb x 80 80 g1 to g80 0 1 0 1 0 176rgb x 88 88 g1 to g88 0 1 0 1 1 176rgb x 96 96 g1 to g96 0 1 1 0 0 176rgb x 104 104 g1 to g104 0 1 1 0 1 176rgb x 112 112 g1 to g112 0 1 1 1 0 176rgb x 120 120 g1 to g120 0 1 1 1 1 176rgb x 128 128 g1 to g128 1 0 0 0 0 176rgb x 136 136 g1 to g136 1 0 0 0 1 176rgb x 144 144 g1 to g144 1 0 0 1 0 176rgb x 152 152 g1 to g152 1 0 0 1 1 176rgb x 160 160 g1 to g160 1 0 1 0 0 176rgb x 168 168 g1 to g168 1 0 1 0 1 176rgb x 176 176 g1 to g176 1 0 1 1 0 176rgb x 184 184 g1 to g184 1 0 1 1 1 176rgb x 192 192 g1 to g192 1 1 0 0 0 176rgb x 200 200 g1 to g200 1 1 0 0 1 176rgb x 208 208 g1 to g208 1 1 0 1 0 176rgb x 216 216 g1 to g216 1 1 0 1 1 176rgb x 224 224 g1 to g224 1 1 1 0 0 176rgb x 232 232 g1 to g232 1 1 1 0 1 176rgb x 240 240 g1 to g240
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 33 display data control (r02h) chs0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 ds1 ds0 0 chs1 0 df1 df0 0 0 rgb1 rgb2 0 0 figure 16. display data control instruction ds1-0 : select relationship between input data type and output data type. table 16. ds bits setting ds1 ds0 input output 0 0 stripe / delta stripe / delta 0 1 delta stripe 1 0 stripe delta 1 1 setting inhibited chs1-0 : select channel length. table 17. chs bits setting chs1 chs0 channel length 0 0 384 (128 rgb) 0 1 480 (160 rgb) 1 0 492 (164 rgb) 1 1 setting inhibited df1-0 : select data format when 8-bit interface (im=1). table 18. df bits setting df1 df0 data format 0 0 rgb rgb 0 1 rgbx rgbx 1 0 xrgb xrgb 1 1 setting inhibited note : rgbx (x: dummy data) rgb1-0 : select rgb data format. table 19. rgb bits setting source output (n=0~163) rgb1 rgb0 s(3n+1) s(3n+2) s(3n+3) 0 0 r g b 0 1 b g r 1 0 g r b 1 1 r b g
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 34 entry mode (r03h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 vpl hpl dpl epl 0 0 ss 0 0 0 0 0 0 stb 0 figure 17. entry mode instruction vspl : reverses the polarity of the vsync signal. vspl= ?0?: vsync is low active. vspl= ?1?: vsync is high active. hspl : reverses the polarity of the hsync signal. hspl= ?0?: hsync is low active. hspl= ?1?: hsync is high active. dpl : reverses the polarity of the dotclk signal. dpl= ?0?: display data is fetched at rising edge of dotclk. dpl= ?1?: display data is fetched at falling edge of dotclk. epl : set the polarity of enable pin while using de interface mode. epl = ?0?: enable = ?low? / write data of pd23-0 enable = ?high? / don?t write data of pd23-0 epl = ?1?: enable = ?high? / write data of pd23-0 enable = ?low? / don?t write data of pd23-0 ss : selects the output shift direction of the source driver. ss= ?0?: s1~s3 ?? s490~s492 ss= ?1?: s490~s492 ?? s1~s3 stb : when stb = 1, S6F2002 enters ?stand-by? mode, where display operation completely stops with halting all the internal operations. further, all the external clock pulses are blocked to prevent unnecessary power consumption. for more information, please refer to the stand-by mode section. only the following instructions can be executed during the stand-by mode. - standby mode cancel (stb = ?0?)
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 35 ss=0,rgb=00 s1 s2 s3 s492 s491 s490 s1 s2 s3 ss=1,rgb=00 s492 s491 s490 ss=0,rgb=01 s1 s2 s3 s492 s491 s490 s1 s2 s3 ss=1,rgb=01 s492 s491 s490 b g r b g r r g b r g b r g b r g b r g b r g b r g b r g b b g r b g r b g r b g r b g r b g r figure 18. display direction according to ss, rgb
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 36 gate control 1 (r04h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 clw2 clw1 clw0 0 0 0 0 0 gaon 0 sdr 0 0 0 figure 19. gate control1 instruction figure 20. clw bits clw2-0 : specify the pulse output timing of the ckv and ckvb signal. table 20. clw bits setting pulse output timing of ckvb (dotclk) clw2 clw1 clw0 24 bit interface ( im=0 ) 8 bit interface ( im=1 ) 0 0 0 0 clock 0 clock 0 0 1 8 clock 24 clock 0 1 0 16 clock 48 clock 0 1 1 24 clock 72 clock 1 0 0 32 clock 96 clock 1 0 1 40 clock 120 clock 1 1 0 48 clock 144 clock 1 1 1 56 clock 168 clock note: the values indicate the number of clocks after the falling edge of ckv & ckvb. gaon : gate all on.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 37 sdr : select odd or even line by stv_l/r, ckv_l/r and ckvb_l/r when double asg(nmd=?1?) sdr = ?0? : stv_r, ckv_r, ckvb_r drive odd line stv_l, ckv_l, ckvb_l drive even line sdr = ?1? : stv_l, ckv_l, ckvb_l drive odd line stv_r, ckv_r, ckvb_r drive even line gate control2 (r05h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 nw1 nw0 0 dsc 0 0 gif fhn 0 fti1 fti0 0 0 fwi1 fwi0 figure 21. gate control2 instruction nw1-0 : specify the number of raster-rows that will alternate in the line inversion waveform. table 21. nw bits setting nw1 nw0 line inversion 0 0 frame inversion 0 1 1-line inversion 1 0 2-line inversion 1 1 setting inhibited 123456 240241242243 255256123456 240241242243 255256 12 ?|?|?| ?|?|?| frame inversion 1 line inversion 2 line inversion 1 frame display region 1 frame display region ... ... figure 22. frame / line inversion timing dsc : specify state of gate control signals (stv_l/r, ckv_l/r, ckvb_l/r). dsc = ?0? : gate control signals are disable. (fixed to vgoff level) dsc = ?1? : gate control signals are enable. (either vgh or vgoff) gif : specify type of gate control signals. gif = ?0? : stv is fixed by fwi, fti and fhn when sync mode (ssmd=0). stv is fixed as width as 2 horizontal period when de mode (ssmd=1). gif = ?1? : stv is fixed as width as 1 horizontal period.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 38 stv ckv ckvb gif=0 2-horizontal period (maximum) 1 - frame stv ckv ckvb gif=1 1-horizontal period 1 - frame figure 23. gate output control waveform1 fhn : specify period of stv when sync mode(ssmd=0). fhn = ?0? : the width of stv is fixed by fwi. fhn = ?1? : the width of stv is fixed as delayed 1h by fti and next 1h. fti1-0 : specify start point of stv when sync mode(ssmd=0). table 22. fti bits setting delay amount fti1 fti0 24 bit i/f 8 bit i/f 0 0 0 clock 0 clock 0 1 7 clock 21 clock 1 0 17 clock 51 clock 1 1 37 clock 111 clock fwi1-0 : specify width of stv when sync mode(ssmd=0). table 23. fwi bits setting width of stv fwi1 fwi0 24 bit i/f 8 bit i/f 0 0 10 clock 30 clock 0 1 40 clock 120 clock 1 0 80 clock 240 clock 1 1 1 h period
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 39 fwi fti fhn=1 clw clw stv ckv ckvb 1 h figure 24. gate output control waveform2 display control1 (r06h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 0 0 0 0 vbp8 vbp7 vbp6 vbp5 vbp4 vbp3 vbp2 vbp1 vbp0 figure 25. display control1 instruction vbp8-0 : vertical back porch. (3h < vbp < 512h) display control2 (r07h) w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 0 0 0 0 hbp8 hbp7 hbp6 hbp5 hbp4 hbp3 hbp2 hbp1 hbp0 hbp9 figure 26. display control2 instruction hbp9-0 : horizontal back porch. (7clock < hbp < 1024clock)
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 40 source output timing control (r08h) 0 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 0 sdt2 sdt1 sdt0 0 0 0 0 eq2 eq1 eq0 0 0 figure 27. source output timing control instruction sdt1-0 : specify the timing on which a source signal is output after falling edge of a gate signal. table 24. sdt bits setting delay amount of the source output (dotclk) sdt2 sdt1 sdt0 24 bit interface ( im=0 ) 8 bit interface ( im=1 ) 0 0 0 0 clock 0 clock 0 0 1 8 clock 24 clock 0 1 0 16 clock 48 clock 0 1 1 24 clock 72 clock 1 0 0 32 clock 96 clock 1 0 1 40 clock 120 clock 1 1 0 48 clock 144 clock 1 1 1 56 clock 168 clock eq2-0 : equalized period is added as specified by bits of eq2-0. the equalization signal is output for ac raster-rows. table 25. eq bits setting equalizing period (dotclk) eq2 eq1 eq0 24 bit interface ( im=0 ) 8 bit interface ( im=1 ) 0 0 0 not equalized not equalized 0 0 1 16 clock 48 clock 0 1 0 32 clock 96 clock 0 1 1 48 clock 144 clock 1 0 0 64 clock 192 clock 1 0 1 80 clock 240 clock 1 1 0 96 clock 288 clock 1 1 1 112 clock 336 clock
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 41 power control 1 (r09h) poc w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 exm 0 0 gon 0 0 0 sap2 sap1 sap0 0 ap2 ap1 ap0 figure 28. power control1 instruction exm : disable all the internal vcom generation circuits such as vcomh / vcoml amplifiers, bias circuits, bleeder resistors, vcomout switching circuit, etc. ?exm? instruction is useful to suppress additional power consumption when S6F2002 works in an external-vcom driving configuration. table 26. exm bit and power block status exm status 0 normal operation 1 disabled the internal vcom generation circuits. blocks status vcomh not generated (opa disabled, hi-z) vcoml not generated (opa disabled, hi-z) vcomout stop switchig (m signal blocked, vcomout: gnd) gon : vcomout level is gnd when gon = 0. table 27. gon bit and vcomout gon vcomout 0 gnd fixed 1 normal operation poc: power control. poc = ?0? : white display poc = ?1? : normal display
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 42 sap2-0: the amount of fixed current from the fixed current source in the operational amplifier for the source driver is adjusted. when the amount of fixed current is large, lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when sap2-0 = ?000?, the current consumption can be reduced by ending the operational amplifier operation. table 28. sap bits setting sap2 sap1 sap0 amount of current in operational amplifier 0 0 0 operation of the operational amplifier stops. 0 0 1 small 0 1 0 small or medium 0 1 1 medium 1 0 0 medium or large 1 0 1 large 1 1 0 setting inhibited 1 1 1 setting inhibited ap2?0: the amount of fixed current in the operational amplifier for the power supply can be adjusted. when the amount of fixed current is large, the lcd driving ability and the display quality become high, but the current consumption is increased. adjust the fixed current considering the display quality and the current consumption. during no display, when ap2-0 = ?000?, the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. table 29. ap bits setting ap2 ap1 ap0 amount of current in operational amplifier 0 0 0 stop operation of the operational amplifiers. 0 0 1 small 0 1 0 small or medium 0 1 1 medium 1 0 0 medium or large 1 0 1 large 1 1 0 setting inhibited 1 1 1 setting inhibited
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 43 power control 2 (r0ah) vdv1 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 vcomg vdv4 vdv3 vdv2 vdv0 0 0 0 vcm4 vcm3 vcm2 vcm1 vcm0 figure 29. power control2 instruction vcomg : when vcomg=0, vcoml voltage is fixed to gnd and internal circuits which make vcoml are disabled. therefore, low power consumption is accomplished. when vcomg = 0, vdv4-0 register setting is invalid. in this case, adjustment of vcomout amplitude is determined only to vcomh by vcm4-0 setting. table 30. vcomg bit and vcoml vcomg vcoml 0 gnd fixed 1 voltage level set by vdv4-0 vdv4-0 : set vcoml voltage which is a lower level voltage of vcomout. vcoml voltage is designated directly by vdv4-0 register value ranging from -1.0v to 1.0v in 32 steps. unit step voltage is around 32mv. table 31. vdv4-0 vs vcoml voltage vdv4 vdv3 vdv2 vdv1 vdv0 vcoml vdv4 vdv3 vdv2 vdv1 vdv0 vcoml 0 0 0 0 0 1.000 v 1 0 0 0 0 -0.032 v 0 0 0 0 1 0.935 v 1 0 0 0 1 -0.097 v 0 0 0 1 0 0.871 v 1 0 0 1 0 -0.161 v 0 0 0 1 1 0.806 v 1 0 0 1 1 -0.226 v 0 0 1 0 0 0.742 v 1 0 1 0 0 -0.290 v 0 0 1 0 1 0.677 v 1 0 1 0 1 -0.355 v 0 0 1 1 0 0.613 v 1 0 1 1 0 -0.419 v 0 0 1 1 1 0.548 v 1 0 1 1 1 -0.484 v 0 1 0 0 0 0.484 v 1 1 0 0 0 -0.548 v 0 1 0 0 1 0.419 v 1 1 0 0 1 -0.613 v 0 1 0 1 0 0.355 v 1 1 0 1 0 -0.677 v 0 1 0 1 1 0.290 v 1 1 0 1 1 -0.742 v 0 1 1 0 0 0.226 v 1 1 1 0 0 -0.806 v 0 1 1 0 1 0.161 v 1 1 1 0 1 -0.871 v 0 1 1 1 0 0.097 v 1 1 1 1 0 -0.935 v 0 1 1 1 1 0.032 v 1 1 1 1 1 -1.000 v
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 44 vcm4-0 : set vcomh voltage which is a upper level voltage of vcomout. vcomh voltage is designated directly by vcm4-0 register value ranging from 3.0v to 4.5v in 32 steps. unit step voltage is about 16mv. table 32. vcm4-0 vs vcomh voltage vcm4 vcm3 vcm2 vcm1 vcm0 vcomh vcm4 vcm3 vcm2 vcm1 vcm0 vcomh 0 0 0 0 0 3.000 v 1 0 0 0 0 3.774 v 0 0 0 0 1 3.048 v 1 0 0 0 1 3.823 v 0 0 0 1 0 3.097 v 1 0 0 1 0 3.871 v 0 0 0 1 1 3.145 v 1 0 0 1 1 3.919 v 0 0 1 0 0 3.194 v 1 0 1 0 0 3.968 v 0 0 1 0 1 3.242 v 1 0 1 0 1 4.016 v 0 0 1 1 0 3.290 v 1 0 1 1 0 4.065 v 0 0 1 1 1 3.339 v 1 0 1 1 1 4.113 v 0 1 0 0 0 3.387 v 1 1 0 0 0 4.161 v 0 1 0 0 1 3.435 v 1 1 0 0 1 4.210 v 0 1 0 1 0 3.484 v 1 1 0 1 0 4.258 v 0 1 0 1 1 3.532 v 1 1 0 1 1 4.306 v 0 1 1 0 0 3.581 v 1 1 1 0 0 4.355 v 0 1 1 0 1 3.629 v 1 1 1 0 1 4.403 v 0 1 1 1 0 3.677 v 1 1 1 1 0 4.452 v 0 1 1 1 1 3.726 v 1 1 1 1 1 4.500 v
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 45 gamma control (r10h to r19h) prp11 w rw rs ib15 ib14 ib13 ib12 ib11 ib10 ib9 ib8 ib7 ib6 ib5 ib4 ib3 ib2 ib1 ib0 1 0 0 0 0 0 prp12 prp10 0 0 0 0 0 prp02 prp01 prp00 prn11 w 1 0 0 0 0 0 prn12 prn10 0 0 0 0 0 prn02 prn01 prn00 vrp11 w 1 0 0 0 vrp14 vrp13 vrp12 vrp10 0 0 0 0 vrp03 vrp02 vrp01 vrp00 vrn11 w 1 0 0 0 vrn14 vrn13 vrn12 vrn10 0 0 0 0 vrn03 vrn02 vrn01 vrn00 pkp11 w 1 0 0 0 0 0 pkp12 pkp10 0 0 0 0 0 pkp02 pkp01 pkp00 pkp31 w 1 0 0 0 0 0 pkp32 pkp30 0 0 0 0 0 pkp22 pkp21 pkp20 pkp51 w 1 0 0 0 0 0 pkp52 pkp50 0 0 0 0 0 pkp52 pkp51 pkp50 pkn11 w 1 0 0 0 0 0 pkn12 pkn10 0 0 0 0 0 pkn02 pkn01 pkn00 pkn31 w 1 0 0 0 0 0 pkn32 pkn30 0 0 0 0 0 pkn22 pkn21 pkn20 pkn51 w 1 0 0 0 0 0 pkn52 pkn50 0 0 0 0 0 pkn52 pkn51 pkn50 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 figure 30. gamma control instruction prp12-00: gradient adjusting register for the positive polarity output. prn12-00: gradient adjusting register for the negative polarity output. vrp14-00: reference / amplitude adjustment register for the positive polarity output. vrn14-00: reference / amplitude adjustment register for the negative polarity output. pkp52?00: gamma micro adjusting register for the positive polarity output. pkn52-00: gamma micro adjusting register for the negative polarity output.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 46 reset function the S6F2002 is initialized by reset input. the reset input must be held for at least 1 ms. instruction set initialization 1. nop 2. driver output control (im=0, nmd=0, ssmd=0, rev=0, nl4-0=11101) 3. lcd driving waveform control (ds1-0=00, chs1-0=00, df1-0=00, rgb1-0=00) 4. entry mode set (vpl=0, hpl=0, dpl=0, epl=0, ss=0, stb=0) 5. display control (1) (clw2-0=000, gaon=0, sdr=0) 6. display control (2) (nw1-0=01, dsc=1, gif=0, fhn=1, fti1-0=10, fwi1-0=11) 7. source output timing control (vbp8-0=000h) 8. external display interface (hbp9-0=000h) 9. panel interface control (sdt2-0=000, eq2-0=000) 10. power control 1 (exm=0, gon=0, poc=0, sap2-0=000, ap2-0=000) 11. power control 2 (vcomg=0, vdv4-0=00000, vcm4-0=00000) 12. gamma control (prp02-00=000, prp12-10=000, prn02-00=000, prn12-10=000, vrp03-00=0000, vrp14-10=00000, vrn03-00=0000, vrn14-10=00000, pkp02?00=000, pkp12?10=000, pkp22?20=000, pkp32?30=000, pkp42?40=000, pkp52?50=000, pkn02?00=000, pkn12?10=000, pkn22?20=000, pkn32?30=000, pkn42?40=000, pkn52?50=000) output pin initialization 1. lcd driver output pins (source output): output high-z level.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 47 interface specification system interface : serial data transfer the S6F2002 initiates serial data transfer by transferring the start byte at the falling edge of csb input. it ends serial data transfer at the rising edge of csb input. the S6F2002 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the S6F2002. the S6F2002, when selected, receives the subsequent data string. the id pin can determine the least significant bit of the identification code. the five upper bits must be 01110. two different chip addresses must be assigned to a single S6F2002 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, data can be written to the index register or status can be read, and when rs = 1, an instruction can be issued. read or write is selected according to the eighth bit of the start byte (r/w bit). the data is received when the r/w bit is 0, and is transmitted when the r/w bit is 1. after receiving the start byte, the S6F2002 receives or transmits the subsequent data byte-by-byte. the data is transferred with the msb first. all S6F2002 instructions are 16 bits. two bytes are received with the msb first, and then the instructions are internally executed. after the start byte has been received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. table 33. start byte format transfer bit s 1 2 3 4 5 6 7 8 device id code start byte format transfer start 0 1 1 1 0 id rs r/w note: id pin selects id bit. table 34. rs and r/w bit function rs rw function 0 0 set index register 0 1 status read 1 0 write instruction 1 1 id read ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 instruction instruction code d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 input 1st transfer(upper) 2nd transfer(lower) ib 15 ib 14 ib 13 ib 12 ib 11 ib 10 ib 9 ib 8 ib 7 ib 6 ib 5 ib 4 ib 3 ib 2 ib 1 ib 0 instruction instruction code d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 input 1st transfer(upper) 2nd transfer(lower) figure 31. instruction of serial data transfer
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 48 procedure for transfer on clock synchronized serial bus interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2 1 22 23 24 1 1 0 id rs r w db db db db db db db db db db db db db db db db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id rs r/w start byte db db db db db db db db db db db db db db db db 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transfer start transfer end scl (input) sdi (input) tso[0] (output) csb (input) 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id index register setting instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 status read instruction figure 32. timing of basic data transfer through clock-synchronized serial bus interface start byte instruction 1: upper instruction 1: lower instruction 2: upper 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 instruction 1: execution time end start note: the first byte after the start byte is always the upper eight bits. scl (input) sdi (input) csb (input) start byte instruction 1: upper instruction 2: upper 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 instruction 1: execution time end start note: the first byte after the start byte is always the upper eight bits. scl (input) sdi (input) (input) figure 33. timing of consecutive data-transfer through clock-sy nchronized serial bus interface start byte rs=1 sdi (input) dummy read 1 upper 8 -bit lower 8 -bit start end (output) csb (input) start byte rw=1 sdi (input) read 1 id read upper 8 -bit lower 8 -bit start end tso[0] (output) scl id read figure 34. id read timing
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 49 24-bit interface 24-bit rgb interface can be used by setting im to 0. display operation is synchronized with vsync, hsync, and dotclk signals. data for display is transferred via 24-bit rgb data bus (pd23-0). input -- bit rgb interface 1- pixel input *16,777,216 -color display is possible using the 24- 1- pixel rgb arrange pd 23 pd 22 pd 21 pd 20 pd 19 pd 18 pd 17 pd 16 pd 15 pd 14 pd 13 pd 12 pd 11 pd 10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 figure 35. rgb data arrangement in the 24-bit interface mode 8-bit interface 8-bit rgb interface can be used by setting im to 1. display operation is synchronized with vsync, hsync, and dotclk signals. data for display is transferred via 8-bit rgb data bus (pd23 to 16) unused pins must be fixed to the gnd level. input -- bit rgb interface 1- pixel input *16,777,216 -color display is possible using the 8 - 1- pixel rgb arrange pd 23 pd 22 pd 21 pd 20 pd 19 pd 18 pd 17 pd 16 r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 pd 23 pd 22 pd 21 pd 20 pd 19 pd 18 pd 17 pd 16 pd 23 pd 22 pd 21 pd 20 pd 19 pd 18 pd 17 pd 16 1st transfer 2nd transfer 3rd transfer figure 36. rgb data arrangement in the 8-bit interface mode
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 50 sync mode interface [24-bit] vsync hsync dotclk pd[23:0] hsync dotclk 7dotclk~10dotclk 1 horizontal period hbp[9:0] > 7 dotclk pd1 pd2 pd3 pd164 pd163 pd[23:0] note : 1. polarity register setting : vpl=0, hpl=0, dpl=0. 2. the rising edge of dotclk is used to fetch displa y data pd bus. 3. channel length : 164r gb (chs[1:0]=10). 164 dotclk valid data transfer area figure 37. 24-bit sync mode interface timing
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 51 sync mode interface [8-bit] vsync hsync dotclk pd[23:16] hsync dotclk 20dotclk~30dotclk 1 horizontal period hbp[9:0] > 20 dotclk pd1 pd[23:16] pd2 pd3 pd164 pd163 b rg b rg b rg b rg b rg note : 1. polarity register setting : v pl=0, hpl=0, dpl=0. 2. the rising edge of dotclk is used to fetch displa y data pd bus. 3. channel length : 164r gb (chs[1:0]=10). valid data transfer area 164 * 3 dotclk figure 38. 8-bit sync mode interface timing notes: 1. three clocks are regarded as one clock for transf er when data is transferred in 8-bit interface. 2. vsync, hsync, dotclk, and pd23-16 should be transferred in units of three clocks.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 52 de mode interface [24-bit] dotclk pd[23:0] dotclk 1 horizontal period pd1 pd2 pd3 pd164 pd163 pd[23:0] note : 1. polarity register setting : epl=0, dpl=0. 2. the rising edge of dotclk is used to fetch displa y data pd bus. 3. channel length : 164r gb (chs[1:0]=10). 164 dotclk valid data transfer area enable enable pd1 pd2 pd3 31 dotclk ~ 80 dotclk 1 vertical period 240 h > 2h dummy enable (2h) figure 39. 24-bit de mode interface timing
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 53 de mode interface [8-bit] dotclk 1 horizontal period pd1 pd[23:16] pd2 pd3 pd164 pd163 b rg b rg b rg b rg b rg note : 1. polarity register setting : epl=0, dpl=0. 2. the rising edge of dotclk is used to fetch displa y data pd bus. 3. channel length : 164r gb (chs[1:0]=10). valid data transfer area enable b rg b rg rg 164 * 3 dotclk 93 dotclk ~ 240 dotclk dotclk pd[23:16] enable 1 vertical period 240 h > 2h dummy enable (2h) figure 40. 8-bit de mode interface timing
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 54 display signal timing display timing in 1 frame 1st line 2nd line 3rd line 4th line vsync hsync dotclk pd[23:0] com stv ckv ckvb sn 1st line 2nd line 3rd line vbp[8:0](r06h) 1st line vbp[8:0](r06h) figure 41. display timing in 1 frame
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 55 display timing in 1 horizontal line clw[2:0] clw[2:0] ckvb ckv hsync com sn dotclk n+1 line data n line output n+2 line data pd[23:0] n+1 line output sdt[2:0] sdt[2:0] figure 42. display timing in 1 horizontal line
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 56 amorphous-silicon gate tft?lcd panel control S6F2002 generates timing signals (stv_l/r, ckv_l/r, and ckvb_l/r) for controlling an amorphous -silicon tft lcd panel with built-in gate driver circuits. S6F2002 also has built-in level shifters for an amorphous-silicon tft lcd panel. output signals table 35. output signals level shifter output signals remarks stv_l/r (output for the frame-start pulse) - ckv_l/r (output for the one-raster-row-cycle pulse) ckvb_l/r (output for the one-raster-row-cycle pulse) the output timing varies by bits of clw2-0. normal asg (nmd=0) 1 horizontal period stv_l ckv_l ckvb_l sn g1 g2 g3 g4 1st line 2nd line 3rd line 4th line figure 43. gate control signal timing in normal asg mode note: lsenl=1, lsenr=0.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 57 double asg (nmd=1) 1 horizontal period stv_l ckv_l ckvb_l sn g1 g2 g3 g4 stv_r ckv_r ckvb_r 1st line 2nd line 3rd line 4th line figure 44. gate control signal timing in double asg mode note: lsenl=1, lsenr=1.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 58 gamma adjustment function S6F2002 provides the gamma adjustment function to display 262,144 colors simultaneously. the gamma adjustment is executed by the gradient adjustment register, the reference adjustment register, the amplitude adjustment resister and the micro-adjustment register that determine the 8 grayscale levels. furthermore, since these registers have the positive polarities and negative polarities, adjust them to match lcd panel respectively. figure 45. grayscale control
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 59 structure of grayscale amplifier the structure of grayscale amplifier is shown as below. the 8 voltage levels (vin0-vin7) between gvdd and vgs are determined by the gradient adjustment register, the reference adjustment register, the amplitude adjustment resister and the micro-adjustment register. each level is split into 8 levels again by the internal ladder resistor network. as a result, grayscale amplifier generates 64 voltage levels ranging from v0 to v63. figure 46. structure of grayscale amplifier
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 60 figure 47. structure of resistor ladder network / 8 to 1 selector
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 61 gamma adjustment register this block has registers to set up the grayscale voltage adjusting to the gamma specification of the lcd panel. these registers can independently set up to positive/negative polarities and there are 4 types of register groups to adjust gradient and amplitude on number of the grayscale, characteristics of the grayscale voltage. (average are common.) the following figure indicates the operation of each adjustment register. grayscale number grayscale voltage a) gradient adjustment grayscale number grayscale voltage b) reference adjustment grayscale number grayscale voltage d) micro-adjustment grayscale number grayscale voltage c) amplitude adjustment figure 48. the operation of adjusting register gradient adjusting resistor the gradient adjustment register is to adjust the gradient in the middle of the grayscale characteristics for the voltage without changing the dynamic range. to accomplish the adjustment, it controls the variable resistor (vrhp(n) / vrlp(n)) of the resistor ladder for the grayscale voltage generator. also, there is an independent register on the positive/negative polarities in order for corresponding to asymmetry drive. reference adjusting resistor the reference adjustment register is to adjust the reference of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp(n)1) of the ladder resistor for the grayscale voltage generator located at the lower side of the resistor ladder. amplitude adjusting resistor the amplitude adjustment register is to adjust the amplitude of the grayscale voltage. to accomplish the adjustment, it controls the variable resistor (vrp(n)0) of the ladder resistor for the grayscale voltage generator located at the upper side of the resistor ladder. micro-adjusting resistor the micro adjustment register is to make subtle adjustment of the grayscale voltage level. to accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the resistor ladder. also, there is an independent register on the positive/negative polarities as well as other adjustment registers.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 62 table 36. gamma adjustment register register positive polarity negative polarity set-up contents prp0[2:0] prn0[2:0] variable resistor vrhp(n) gradient adjustment prp1[2:0] prn1[2:0] variable resistor vrlp(n) reference adjustment vrp1[4:0] vrn1[4:0] variable resistor vrp(n)1 amplitude adjustment vrp0[3:0] vrn0[3:0] variable resistor vrp(n)0 pkp0[2:0] pkn0[2:0] the voltage of grayscale number 1 is selected by the 8 to 1 selector pkp1[2:0] pkn1[2:0] the voltage of grayscale number 8 is selected by the 8 to 1 selector pkp2[2:0] pkn2[2:0] the voltage of grayscale number 20 is selected by the 8 to 1 selector pkp3[2:0] pkn3[2:0] the voltage of grayscale number 43 is selected by the 8 to 1 selector pkp4[2:0] pkn4[2:0] the voltage of grayscale number 55 is selected by the 8 to 1 selector micro adjustment pkp5[2:0] pkn5[2:0] the voltage of grayscale number 62 is selected by the 8 to 1 selector
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 63 ladder resistor network / 8 to 1 selector this block outputs the reference voltage of the grayscale voltage. there are two ladder resistors including the variable resistor and the 8 to 1 selector selecting voltage generated by the ladder resistance voltage. the variable and 8 to 1 resistors are controlled by the gamma resistor. also, there are pins that connect to the external volume resistor. in addition, it allows compensating the dispersion of length between one panel and another. variable resistor there are 4 types of the variable resistors that are for the gradient adjustment (vrhp(n) / vrlp(n)) and for the reference / amplitude adjustment (vrp(n)1 / vrp(n)0). the resistance value is set by the gradient adjustment register and the reference / amplitude adjustment registers as below. table 37. gradient adjustment (1) register value prp(n)0 [2:0] resistance value vrhp(n) 000 0r 001 4r 010 8r 011 12r 100 16r 101 20r 110 24r 111 28r table 38. gradient adjustment (2) register value prp(n)1 [2:0] resistance value vrlp(n) 000 0r 001 4r 010 8r 011 12r 100 16r 101 20r 110 24r 111 28r table 39. reference adjustment register value vrp(n)1[4:0] resistance value vrp(n)1 00000 0r 00001 1r 00010 2r . . . . . . 11101 29r 11110 30r 11111 31r
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 64 table 40. amplitude adjustment register value vrp(n)0 [3:0] resistance value vrp(n)0 0000 0r 0001 2r 0010 4r . . . . . . 1101 26r 1110 28r 1111 30r the 8 to 1 selector in the 8-to-1 selector, the voltage level must be selected by the given ladder resistance and the micro-adjustment register and output the six types of the reference voltage, vin1 to vin6. following figure explains the relationship between the micro-adjustment register and the selected voltage. table 41. relationship between micro-adjustment register and selected voltage selected voltage register value pkp(n) [2:0] vinp(n)1 vinp(n)2 vinp(n)3 vinp(n)4 vinp(n)5 vinp(n)6 000 kvp(n)1 kvp(n)9 kvp(n)17 kvp(n)25 kvp(n)33 kvp(n)41 001 kvp(n)2 kvp(n)10 kvp(n)18 kvp(n)26 kvp(n)34 kvp(n)42 010 kvp(n)3 kvp(n)11 kvp(n)19 kvp(n)27 kvp(n)35 kvp(n)43 011 kvp(n)4 kvp(n)12 kvp(n)20 kvp(n)28 kvp(n)36 kvp(n)44 100 kvp(n)5 kvp(n)13 kvp(n)21 kvp(n)29 kvp(n)37 kvp(n)45 101 kvp(n)6 kvp(n)14 kvp(n)22 kvp(n)30 kvp(n)38 kvp(n)46 110 kvp(n)7 kvp(n)15 kvp(n)23 kvp(n)31 kvp(n)39 kvp(n)47 111 kvp(n)8 kvp(n)16 kvp(n)24 kvp(n)32 kvp(n)40 kvp(n)48 the grayscale levels are determined by the following formulas listed in the next pages.
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 65 table 42. formulas for calculating gamma adjusting voltage (positive polarity) 1 pins formula micro-adjusting register value reference voltage kvp0 gvdd- ? v*vrp0/sumrp - vinp0 kvp1 gvdd- ? v*(vrp0+5r)/sumrp pkp0[2:0] = ?000? kvp2 gvdd- ? v*(vrp0+9r)/sumrp pkp0[2:0] = ?001? kvp3 gvdd- ? v*(vrp0+13r)/sumrp pkp0[2:0] = ?010? kvp4 gvdd- ? v*(vrp0+17r)/sumrp pkp0[2:0] = ?011? kvp5 gvdd- ? v*(vrp0+21r)/sumrp pkp0[2:0] = ?100? kvp6 gvdd- ? v*(vrp0+25r)/sumrp pkp0[2:0] = ?101? kvp7 gvdd- ? v*(vrp0+29r)/sumrp pkp0[2:0] = ?110? kvp8 gvdd- ? v*(vrp0+33r)/sumrp pkp0[2:0] = ?111? vinp1 kvp9 gvdd- ? v*(vrp0+33r+vrhp)/sumrp pkp1[2:0] = ?000? kvp10 gvdd- ? v*(vrp0+34r+vrhp)/sumrp pkp1[2:0] = ?001? kvp11 gvdd- ? v*(vrp0+35r+vrhp)/sumrp pkp1[2:0] = ?010? kvp12 gvdd- ? v*(vrp0+36r+vrhp)/sumrp pkp1[2:0] = ?011? kvp13 gvdd- ? v*(vrp0+37r+vrhp)/sumrp pkp1[2:0] = ?100? kvp14 gvdd- ? v*(vrp0+38r+vrhp)/sumrp pkp1[2:0] = ?101? kvp15 gvdd- ? v*(vrp0+39r+vrhp)/sumrp pkp1[2:0] = ?110? kvp16 gvdd- ? v*(vrp0+40r+vrhp)/sumrp pkp1[2:0] = ?111? vinp2 kvp17 gvdd- ? v*(vrp0+45r+vrhp)/sumrp pkp2[2:0] = ?000? kvp18 gvdd- ? v*(vrp0+46r+vrhp)/sumrp pkp2[2:0] = ?001? kvp19 gvdd- ? v*(vrp0+47r+vrhp)/sumrp pkp2[2:0] = ?010? kvp20 gvdd- ? v*(vrp0+48r+vrhp)/sumrp pkp2[2:0] = ?011? kvp21 gvdd- ? v*(vrp0+49r+vrhp)/sumrp pkp2[2:0] = ?100? kvp22 gvdd- ? v*(vrp0+50r+vrhp)/sumrp pkp2[2:0] = ?101? kvp23 gvdd- ? v*(vrp0+51r+vrhp)/sumrp pkp2[2:0] = ?110? kvp24 gvdd- ? v*(vrp0+52r+vrhp)/sumrp pkp2[2:0] = ?111? vinp3 kvp25 gvdd- ? v*(vrp0+68r+vrhp)/sumrp pkp3[2:0] = ?000? kvp26 gvdd- ? v*(vrp0+69r+vrhp)/sumrp pkp3[2:0] = ?001? kvp27 gvdd- ? v*(vrp0+70r+vrhp)/sumrp pkp3[2:0] = ?010? kvp28 gvdd- ? v*(vrp0+71r+vrhp)/sumrp pkp3[2:0] = ?011? kvp29 gvdd- ? v*(vrp0+72r+vrhp)/sumrp pkp3[2:0] = ?100? kvp30 gvdd- ? v*(vrp0+73r+vrhp)/sumrp pkp3[2:0] = ?101? kvp31 gvdd- ? v*(vrp0+74r+vrhp)/sumrp pkp3[2:0] = ?110? kvp32 gvdd- ? v*(vrp0+75r+vrhp)/sumrp pkp3[2:0] = ?111? vinp4 kvp33 gvdd- ? v*(vrp0+80r+vrhp)/sumrp pkp4[2:0] = ?000? kvp34 gvdd- ? v*(vrp0+81r+vrhp)/sumrp pkp4[2:0] = ?001? kvp35 gvdd- ? v*(vrp0+82r+vrhp)/sumrp pkp4[2:0] = ?010? kvp36 gvdd- ? v*(vrp0+83r+vrhp)/sumrp pkp4[2:0] = ?011? kvp37 gvdd- ? v*(vrp0+84r+vrhp)/sumrp pkp4[2:0] = ?100? kvp38 gvdd- ? v*(vrp0+85r+vrhp)/sumrp pkp4[2:0] = ?101? kvp39 gvdd- ? v*(vrp0+86r+vrhp)/sumrp pkp4[2:0] = ?110? kvp40 gvdd- ? v*(vrp0+87r+vrhp)/sumrp pkp4[2:0] = ?111? vinp5 kvp41 gvdd- ? v*(vrp0+87r+vrhp+vrlp)/sumrp pkp5[2:0] = ?000? kvp42 gvdd- ? v*(vrp0+91r+vrhp+vrlp)/sumrp pkp5[2:0] = ?001? kvp43 gvdd- ? v*(vrp0+95r+vrhp+vrlp)/sumrp pkp5[2:0] = ?010? kvp44 gvdd- ? v*(vrp0+99r+vrhp+vrlp)/sumrp pkp5[2:0] = ?011? kvp45 gvdd- ? v*(vrp0+103r+vrhp+vrlp)/sumrp pkp5[2:0] = ?100? kvp46 gvdd- ? v*(vrp0+107r+vrhp+vrlp)/sumrp pkp5[2:0] = ?101? kvp47 gvdd- ? v*(vrp0+111r+vrhp+vrlp)/sumrp pkp5[2:0] = ?110? kvp48 gvdd- ? v*(vrp0+115r+vrhp+vrlp)/sumrp pkp5[2:0] = ?111? vinp6 kvp49 gvdd- ? v*(vrp0+120r+vrhp+vrlp)/sumrp - vinp7 sumrp: total of the positive polarity ladder resistance = vrp0 + 128r + vrhp + vrlp + vrp1 sumrn: total of the negative polarity ladder resistance = vrn0 + 128r + vrhn + vrln + vrn1 ? v: electric potential difference between gvdd and vgs = gvdd*[sumrp(n)/([sumrp(n)+exvr])
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 66 table 43. formulas for calculating gamma adjusting voltage (positive polarity) 2 grayscale voltage formula grayscale voltage formula v0 vinp0 v32 v20-(v20-v43)*(12/23) v1 vinp1 v33 v20-(v20-v43)*(13/23) v2 v1-(v1-v8)*(28/96) v34 v20-(v20-v43)*(14/23) v3 v1-(v1-v8)*(42/96) v35 v20-(v20-v43)*(15/23) v4 v1-(v1-v8)*(60/96) v36 v20-(v20-v43)*(16/23) v5 v1-(v1-v8)*(69/96) v37 v20-(v20-v43)*(17/23) v6 v1-(v1-v8)*(78/96) v38 v20-(v20-v43)*(18/23) v7 v1-(v1-v8)*(87/96) v39 v20-(v20-v43)*(19/23) v8 vinp2 v40 v20-(v20-v43)*(20/23) v9 v8-(v8-v20)*(2/24) v 41 v20-(v20-v43)*(21/23) v10 v8-(v8-v20)*(4/24) v 42 v20-(v20-v43)*(22/23) v11 v8-(v8-v20)*(6/24) v43 vinp4 v12 v8-(v8-v20)*(8/24) v 44 v43-(v43-v55)*(2/24) v13 v8-(v8-v20)*(10/24) v45 v43-(v43-v55)*(4/24) v14 v8-(v8-v20)*(12/24) v46 v43-(v43-v55)*(6/24) v15 v8-(v8-v20)*(14/24) v47 v43-(v43-v55)*(8/24) v16 v8-(v8-v20)*(16/24) v48 v43-(v43-v55)*(10/24) v17 v8-(v8-v20)*(18/24) v49 v43-(v43-v55)*(12/24) v18 v8-(v8-v20)*(20/24) v50 v43-(v43-v55)*(14/24) v19 v8-(v8-v20)*(22/24) v51 v43-(v43-v55)*(16/24) v20 vinp3 v52 v43-(v43-v55)*(18/24) v21 v20-(v20-v43)*(1/23) v53 v43-(v43-v55)*(20/24) v22 v20-(v20-v43)*(2/23) v54 v43-(v43-v55)*(22/24) v23 v20-(v20-v43)*(3/23) v55 vinp5 v24 v20-(v20-v43)*(4/23) v56 v55-(v55-v62)*(9/96) v25 v20-(v20-v43)*(5/23) v57 v55-(v55-v62)*(18/96) v26 v20-(v20-v43)*(6/23) v58 v55-(v55-v62)*(27/96) v27 v20-(v20-v43)*(7/23) v59 v55-(v55-v62)*(36/96) v28 v20-(v20-v43)*(8/23) v60 v55-(v55-v62)*(54/96) v29 v20-(v20-v43)*(9/23) v61 v55-(v55-v62)*(68/96) v30 v20-(v20-v43)*(10/23) v62 vinp6 v31 v20-(v20-v43)*(11/23) v63 vinp7
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 67 table 44. formulas for calculating gamma adjusting voltage (negative polarity) 1 pins formula micro-adjusting register value reference voltage kvn0 gvdd- ? v*vrn0/sumrn - vinn0 kvn1 gvdd- ? v*(vrn0+5r)/sumrn pkn0[2:0] = ?000? kvn2 gvdd- ? v*(vrn0+9r)/sumrn pkn0[2:0] = ?001? kvn3 gvdd- ? v*(vrn0+13r)/sumrn pkn0[2:0] = ?010? kvn4 gvdd- ? v*(vrn0+17r)/sumrn pkn0[2:0] = ?011? kvn5 gvdd- ? v*(vrn0+21r)/sumrn pkn0[2:0] = ?100? kvn6 gvdd- ? v*(vrn0+25r)/sumrn pkn0[2:0] = ?101? kvn7 gvdd- ? v*(vrn0+29r)/sumrn pkn0[2:0] = ?110? kvn8 gvdd- ? v*(vrn0+33r)/sumrn pkn0[2:0] = ?111? vinn1 kvn9 gvdd- ? v*(vrn0+33r+vrhn)/sumrn pkn1[2:0] = ?000? kvn10 gvdd- ? v*(vrn0+34r+vrhn)/sumrn pkn1[2:0] = ?001? kvn11 gvdd- ? v*(vrn0+35r+vrhn)/sumrn pkn1[2:0] = ?010? kvn12 gvdd- ? v*(vrn0+36r+vrhn)/sumrn pkn1[2:0] = ?011? kvn13 gvdd- ? v*(vrn0+37r+vrhn)/sumrn pkn1[2:0] = ?100? kvn14 gvdd- ? v*(vrn0+38r+vrhn)/sumrn pkn1[2:0] = ?101? kvn15 gvdd- ? v*(vrn0+39r+vrhn)/sumrn pkn1[2:0] = ?110? kvn16 gvdd- ? v*(vrn0+40r+vrhn)/sumrn pkn1[2:0] = ?111? vinn2 kvn17 gvdd- ? v*(vrn0+45r+vrhn)/sumrn pkn2[2:0] = ?000? kvn18 gvdd- ? v*(vrn0+46r+vrhn)/sumrn pkn2[2:0] = ?001? kvn19 gvdd- ? v*(vrn0+47r+vrhn)/sumrn pkn2[2:0] = ?010? kvn20 gvdd- ? v*(vrn0+48r+vrhn)/sumrn pkn2[2:0] = ?011? kvn21 gvdd- ? v*(vrn0+49r+vrhn)/sumrn pkn2[2:0] = ?100? kvn22 gvdd- ? v*(vrn0+50r+vrhn)/sumrn pkn2[2:0] = ?101? kvn23 gvdd- ? v*(vrn0+51r+vrhn)/sumrn pkn2[2:0] = ?110? kvn24 gvdd- ? v*(vrn0+52r+vrhn)/sumrn pkn2[2:0] = ?111? vinn3 kvn25 gvdd- ? v*(vrn0+68r+vrhn)/sumrn pkn3[2:0] = ?000? kvn26 gvdd- ? v*(vrn0+69r+vrhn)/sumrn pkn3[2:0] = ?001? kvn27 gvdd- ? v*(vrn0+70r+vrhn)/sumrn pkn3[2:0] = ?010? kvn28 gvdd- ? v*(vrn0+71r+vrhn)/sumrn pkn3[2:0] = ?011? kvn29 gvdd- ? v*(vrn0+72r+vrhn)/sumrn pkn3[2:0] = ?100? kvn30 gvdd- ? v*(vrn0+73r+vrhn)/sumrn pkn3[2:0] = ?101? kvn31 gvdd- ? v*(vrn0+74r+vrhn)/sumrn pkn3[2:0] = ?110? kvn32 gvdd- ? v*(vrn0+75r+vrhn)/sumrn pkn3[2:0] = ?111? vinn4 kvn33 gvdd- ? v*(vrn0+80r+vrhn)/sumrn pkn4[2:0] = ?000? kvn34 gvdd- ? v*(vrn0+81r+vrhn)/sumrn pkn4[2:0] = ?001? kvn35 gvdd- ? v*(rn0+82r+vrhn)/sumrn pkn4[2:0] = ?010? kvn36 gvdd- ? v*(vrn0+83r+vrhn)/sumrn pkn4[2:0] = ?011? kvn37 gvdd- ? v*(vrn0+84r+vrhn)/sumrn pkn4[2:0] = ?100? kvn38 gvdd- ? v*(vrn0+85r+vrhn)/sumrn pkn4[2:0] = ?101? kvn39 gvdd- ? v*(vrn0+86r+vrhn)/sumrn pkn4[2:0] = ?110? kvn40 gvdd- ? v*(vrn0+87r+vrhn)/sumrn pkn4[2:0] = ?111? vinn5 kvn41 gvdd- ? v*(vrn0+87r+vrhn+vrln)/sumrn pkn5[2:0] = ?000? kvn42 gvdd- ? v*(vrn0+91r+vrhn+vrln)/sumrn pkn5[2:0] = ?001? kvn43 gvdd- ? v*(vrn0+95r+vrhn+vrln)/sumrn pkn5[2:0] = ?010? kvn44 gvdd- ? v*(vrn0+99r+vrhn+vrln)/sumrn pkn5[2:0] = ?011? kvn45 gvdd- ? v*(vrn0+103r+vrhn+vrln)/sumrn pkn5[2:0] = ?100? kvn46 gvdd- ? v*(vrn0+107r+vrhn+vrln)/sumrn pkn5[2:0] = ?101? kvn47 gvdd- ? v*(vrn0+111r+vrhn+vrln)/sumrn pkn5[2:0] = ?110? kvn48 gvdd- ? v*(vrn0+115r+vrhn+vrln)/sumrn pkn5[2:0] = ?111? vinn6 kvn49 gvdd- ? v*(vrn0+120r+vrhn+vrln)/sumrn - vinn7 sumrp: total of the positive polarity ladder resistance = vrp0 + 128r + vrhp + vrlp + vrp1 sumrn: total of the negative polarity ladder resistance = vrn0 + 128r + vrhn + vrln + vrn1 ? v: electric potential difference between gvdd and vgs = gvdd*[sumrp(n)/([sumrp(n)+exvr)]
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 68 table 45. formulas for calculating gamma adjusting voltage (negative polarity) 2 grayscale voltage formula grayscale voltage formula v0 vinn0 v32 v20-(v20-v43)*(12/23) v1 vinn1 v33 v20-(v20-v43)*(13/23) v2 v1-(v1-v8)*(28/96) v34 v20-(v20-v43)*(14/23) v3 v1-(v1-v8)*(42/96) v35 v20-(v20-v43)*(15/23) v4 v1-(v1-v8)*(60/96) v36 v20-(v20-v43)*(16/23) v5 v1-(v1-v8)*(69/96) v37 v20-(v20-v43)*(17/23) v6 v1-(v1-v8)*(78/96) v38 v20-(v20-v43)*(18/23) v7 v1-(v1-v8)*(87/96) v39 v20-(v20-v43)*(19/23) v8 vinn2 v40 v20-(v20-v43)*(20/23) v9 v8-(v8-v20)*(2/24) v 41 v20-(v20-v43)*(21/23) v10 v8-(v8-v20)*(4/24) v 42 v20-(v20-v43)*(22/23) v11 v8-(v8-v20)*(6/24) v43 vinn4 v12 v8-(v8-v20)*(8/24) v 44 v43-(v43-v55)*(2/24) v13 v8-(v8-v20)*(10/24) v45 v43-(v43-v55)*(4/24) v14 v8-(v8-v20)*(12/24) v46 v43-(v43-v55)*(6/24) v15 v8-(v8-v20)*(14/24) v47 v43-(v43-v55)*(8/24) v16 v8-(v8-v20)*(16/24) v48 v43-(v43-v55)*(10/24) v17 v8-(v8-v20)*(18/24) v49 v43-(v43-v55)*(12/24) v18 v8-(v8-v20)*(20/24) v50 v43-(v43-v55)*(14/24) v19 v8-(v8-v20)*(22/24) v51 v43-(v43-v55)*(16/24) v20 vinn3 v52 v43-(v43-v55)*(18/24) v21 v20-(v20-v43)*(1/23) v53 v43-(v43-v55)*(20/24) v22 v20-(v20-v43)*(2/23) v54 v43-(v43-v55)*(22/24) v23 v20-(v20-v43)*(3/23) v55 vinn5 v24 v20-(v20-v43)*(4/23) v56 v55-(v55-v62)*(9/96) v25 v20-(v20-v43)*(5/23) v57 v55-(v55-v62)*(18/96) v26 v20-(v20-v43)*(6/23) v58 v55-(v55-v62)*(27/96) v27 v20-(v20-v43)*(7/23) v59 v55-(v55-v62)*(36/96) v28 v20-(v20-v43)*(8/23) v60 v55-(v55-v62)*(54/96) v29 v20-(v20-v43)*(9/23) v61 v55-(v55-v62)*(68/96) v30 v20-(v20-v43)*(10/23) v62 vinn6 v31 v20-(v20-v43)*(11/23) v63 vinn7
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 69 negative polarity positive polarity v0 v63 000000 v0 v63 input data (common characteristics to rgb) 000000 v0 v63 000000 v0 v63 output level 000000 111111 rev=0 figure 49. relationship between input data and output voltage positive polarity negative polarity sn vcomout figure 50. relationship between source driver output and vcomout
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 70 power supply setup flow apply the power in a sequence as shown in figure 52. the settling time of internally-generated voltage levels and analog circuit block such as operational amplifier depend on the value of external resistor or capacitor. more than 10ms (settling time for logic circuits) power on power-on reset display off state at least 1ms gon=0 poc=0 exm, vcomg, vdv [4:0], vcm [4:0] issues instructions for power supply setting 2 ap [2:0], sap [2:0] issues instructions for other mode setting display on sequence* display on gon=1 poc=1 more than 50ms (settling time for the internal op-amps) power-up sequence power-down sequence issues instructions for power supply setting 1 at least 50ms normal display display off sequence* at least 1ms gon=0 poc=0 vcomg=0 issues instructions for power down setting 2 ap [2:0]=000 power off issues instructions for power down setting 1 figure 51. power supply setup flow
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 71 instruction setup flow display on / off sequence display on state gon=1 poc=1 dsc=1 normal operation state wait (more than 2 frames) display off state gon=0 poc=0 dsc=0 display off state gon=0 poc=0 dsc=0 complete power settings wait (more than 2 frames) display on state gon=1 poc=1 dsc=1 display on display-off sequence display off display-on sequence figure 52. display on / off sequence
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 72 stand-by mode in / out sequence figure 53. stand-by mode in / out sequence
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 73 n-raster-row reversed ac drive the S6F2002 supports not only the lcd reversed ac drive in a one-frame unit but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from 1 to 2 raster-rows. when a problem affecting display quality occurs, the n-raster-row reversed ac drive can improve the quality. determine the number of the raster-rows n (nw bit set value) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-row is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. figure 54. example of an ac signal under n-raster-row reversed ac drive
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 74 ac timing following diagram indicates the ac timing on the each ac drive method. after every 1 drawing, the ac timing is occurred on the reversed frame ac drive. after the ac timing, the blank (all outputs from the gate: vgoff output) in 16h period is inserted. when the reversed n-raster-row is driving, a blank period of the 16h period is inserted after all screens are drawn. figure 55. ac timing
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 75 electrical spec ifications absolute maximum ratings table 46. absolute maximum rating (vss = 0v) item symbol rating unit supply voltage for logic circuit vdd - 0.3 ~ + 5.0 v supply voltage for logic i/f circuit vdd3 - 0.3 ~ + 5.0 v supply voltage for internal analog circuit vci - 0.3 ~ + 5.0 v supply voltage for lcd driving circuit avdd - 0.3 ~ + 7.0 v logic input voltage range vin - 0.3 to vdd +0.5 v operating temperature t opr -40 ~ +85 c storage temperature t stg -55 ~ +110 c notes: 1. absolute maximum rating is the limit value beyond which the ic may be broken permanently. they do not assure operations. 2. operating temperature is the rang e of device-operating temperature. they do not guarantee chip performance. 3. absolute maximum rating is guaranteed only when our company?s package used.
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 76 dc characteristics table 47. dc characteristics for power system (vdd= 2.0v, vdd3= vci= 3.0v, vss= 0v, temp= -40?c ~ +85?c) characteristic symbol condition min typ max unit notes power supply for internal logic circuit vdd - 1.8 - 2.5 v power supply for logic interface circuit vdd3 - 1.8 - 3.3 v power supply for internal analog circuit vci - 2.5 - 3.3 v power supply for lcd driving circuit avdd - 4.0 - 5.0 v power supply 1 for asg level shifter vgh ?high? level - 18.0 - v power supply 2 for asg level shifter vgl ?low? level - -10.0 - v generated power for vcoml circuit vcl |vcl| = 0.2 x |vgl| - -2.0 - v generated power for asg level shifter vgoff |vgoff| = 0.7 x |vgl| |vgh-vgoff| max = 25v - -7.0 - v *1 regulated power for internal logic circuit rvdd - - 2.0 - v *2 high v ih - 0.8*vdd3 - vdd3 v logic input voltage low v il - 0 - 0.2*vdd3 v high v oh i oh = -2.0ma vdd3-0.5 vdd3 v logic output voltage low v ol i ol = 2.0ma 0.0 - 0.5 v input leakage current i il vin = vss or vdd3 -1.0 - 1.0 a output leakage current i ol vin = vss or vdd3 -3.0 - 3.0 a output voltage for vcomout high level vcomh set by vcm4-0 register 3.0 - 4.5 v output voltage for vcomout low level vcoml set by vdv4-0 register -1.0 - 1.0 v
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 77 table 48. dc characteristics for lcd driver outputs (vdd= 2.0v, vdd3= vci= 3.0v, vss= 0v, temp= -40?c ~ +85?c) characteristic symbol condition min typ max unit notes lcd gate driver output on resistance ron |vgh-vgoff| =25v vgh=18v, vgl=-10v - - 2 ? lcd source driver high-level output current i hog vso=4.5v vsx=3.5v - - -100 ? *3 lcd source driver low-level output current i log vso=0.5v vsx=1.5v 100 - - ? *3 4.2v vso - 24 50 ? *3 0.8v < vso < 4.2v - 15 30 ? *3 output voltage deviation (in single chip) ? vo vso 0.8v - 28 55 ? *3 4.2v vso - 25 50 ? *3 0.8v < vso < 4.2v - 15 30 ? *3 averaged output voltage deviation (between chip to chip) ? vd vso 0.8v - 23 45 ? *3 lcd source driver output voltage range vso - avss+0.1 - gvdd-0.1 v lcd source driver delay t sd avdd=gvdd=5.0v, sap=?100? - - 40 ? ivdd - t.b.d. t.b.d. ? current consumption during normal operation ivci no load - t.b.d. t.b.d. ma *4 notes: 1. keep | vgoff ? vgl | greater than or equa l to 3.0v when | vgh ? vgoff | = 25.0v 2. rvdd is used in vcomh / vcoml generation block as a reference voltage named rvdd_ref. 3. vsx is the voltage applied to analog output pins s1 to s4 92. vso is the output voltage of analog output pins s1 to s492. 4. vdd3=vci=3.0v, vdd=2.0v, avdd= 5.0v, vgh= 18.0v, vgl= -10.0v, nl[4:0]="11101", ap[2:0]=?001?, sap[2:0]="001", vcomg=?h?, exm=?l?, vcm4-0="11000", vdv4-0=11000".
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 78 ac characteristics table 49. rgb data interface characteristics (t a = -40 to +85 o c) 24bit rgb interface 8bit rgb interface vdd3 = 1.8v to 3.3v vdd3 = 1.8v to 3.3v characteristic symbol min. max. min. max. unit dotclk cycle time t dcyc 100 - 30 - dotclk rise / fall time t r , t f - t.b.d - t.b.d dotclk pulse width high t dchw t.b.d - t.b.d - dotclk pulse width low t dclw t.b.d - t.b.d - enable setup time t ens t.b.d - t.b.d - enable hold time t enh t.b.d - t.b.d - pd data setup time t pds t.b.d - t.b.d - pd data hold time t pdh t.b.d - t.b.d - ns figure 56. ac characteristics (de mode)
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 79 table 50. clock synchronized serial mode characteristics (t a = -40 to +85 o c) vdd3 = 1.8v to 3.3v characteristic symbol min. max. unit serial clock cycle time tscyc t.b.d. - serial clock rise / fall time t r , t f - t.b.d. pulse width high for write t schw t.b.d. - pulse width high for read t schr t.b.d. - pulse width low for write t sclw t.b.d. - pulse width low for read t sclr t.b.d. - chip select setup time t css t.b.d. - chip select hold time t csh t.b.d. - serial input data setup time t sids t.b.d. - serial input data hold time t sidh t.b.d. - serial output data delay time t sodd - t.b.d. serial output data hold time t sodh t.b.d. - ns table 51. reset timing characteristics (t a = -40 to +85 o c) vdd3 = 1.8v to 3.3v characteristic symbol min. max. unit reset low pulse width t res 3* - us * note . reset low pulse width shorter than 1us do not make reset. it means undesired short pulse such as glitch, bouncing noise or electrostatic discharge do not cause irregular system reset. please refer to the table below. table 52. reset operation regarding tres pulse width tres pulse action shorter than 1 us no reset longer than 3 us reset between 1 us and 3 us not determined
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 80 transfer start voh1 vol1 vil vih vil voh1 vol1 vih tsids tsidh tsodh scl sdi tso[0] vil vil vih vih vil vil vih vih csb vih vil tsodd tcss tcsh tr tf tschw / tschr tsclw / tsclr tscyc input data input data output data output data transfer end figure 57. ac characteristics (spi mode) tres resetb vil vil figure 58. ac characteristics (reset timing)
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 81 amorphous-silicon gate level shifter table 53. ac characteristics (stv) (t a = -40 to +85 o c) characteristic symbol condition min. typ. max. unit input frequency fin - - 125 khz propagation delay time td1 / td2 cl= 50pf - 240 420 ns output rising / falling time tr / tf cl= 50pf - 60 100 ns output delay time td3 cl= 50pf - 270 470 ns table 54. ac characteristics (ckv, ckvb) (t a = -40 to +85 o c) parameter symbol condition min. typ. max. unit input frequency fin - - 125 khz propagation delay time td1 / td2 cl= 300pf - 240 420 ns output rising / falling time tr / tf cl= 300pf - 240 420 ns output delay time td3 cl= 300pf - 360 630 ns level shifter input level shifter output 50% 50% 10% 90% 90% td1 td2 tr tf 10% 50% td3 figure 59. level shifter input / output waveform and ac timing
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 82 data-shift direction settings channel selection setting table 55. panel application examples under the various chs1-0 setting chs1-0 configurations ?00? (128 rgb) tft panel (ss=0) bump view s1 s384 tft panel (ss=1) bump view s1 s384 ?01? (160 rgb) tft panel (ss=0) bump view s1 s480 tft panel (ss=1) bump view s1 s480 ?10? (164 rgb) tft panel (ss=0) bump view s1 s492 tft panel (ss=1) bump view s1 s492
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 83 master-slave configuration setting panel (dssel=1, ss=0) master slave s1 s960 ms=0 lsenl=1 lsenr=0 ms=1 lsenl=0 lsenr=1 panel (dssel=1, ss=1) slave master s1 s960 ms=1 lsenl=1 lsenr=0 ms=0 lsenl=0 lsenr=1 s1 s480 s1 s480 s1 s480 s1 s480 cf> drivers showed at the top-side view (bump view). figure 60 . master - slave application setting example
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 84 ito / fpc application example figure 61. ito/fpc application schematic
S6F2002 492-channel source driver with power circuit for 16.7m colors asg tft-lcd preliminary 85 cf> operating conditions of example circui t in previous page are as below : ? applied voltage (external) ? vdd to vss = 3.0 v ? vci to vss = 3.0 v ? avdd to vss = 5.0 v ? vgh to vss = 18.0 v ? vgl to vss = -10.0 v ? interface mode ? data width : 24-bit parallel mode ? resolution : 492-channel * 240 line single chip mode ? scanning : double asg mode
492-channel source driver with power circuit for 16.7m colors asg tft-lcd S6F2002 preliminary 86 notice precautions for light light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. consequently, the users of the packages which may expose chips to external light such as cob, cog, tcp and cof must consider effective methods to block out light from reaching the ic on all parts of the surface area, the top, bottom and the sides of the chip. follow the precautions below when using the products. 1. consider and verify the protection of penetrating light to the ic at substrate (board or glass) or product design stage. 2. always test and inspect products under the environment with no penetration of light.

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